Algorithms for Synthesis and Testing of Asynchronous Circuits
Published on 30. June 1993
Book
Hardback
XIX, 339 pages
978-0-7923-9364-1 (ISBN)
Description
Since the second half of the 1980s asynchronous circuits have been the subject of a great deal of research following a period of relative oblivion. The lack of interest in asynchronous techniques was motivated by the progressive shift towards synchronous design techniques that had much more structure and were much easier to verify and synthesize. System design requirements made it impossible to eliminate totally the use of asynchronous circuits. Given the objective difficulty encountered by designers, the asynchronous components of electronic systems such as interfaces became a serious bottleneck in the design process. The use of new models and some theoretical breakthroughs made it possible to develop asynchronous design techniques that were reliable and effective. This book describes a variety of mathematical models and of algorithms that form the backbone and the body of a new design methodology for asyn chronous design. The book is intended for asynchronous hardware designers, for computer-aided tool experts, and for digital designers interested in ex ploring the possibility of designing asynchronous circuits. It requires a solid mathematical background in discrete event systems and algorithms. While the book has not been written as a textbook, nevertheless it could be used as a reference book in an advanced course in logic synthesis or asynchronous design.
More details
Series
Edition
1993 ed.
Language
English
Place of publication
New York
United States
Target group
Professional and scholarly
Research
Illustrations
XIX, 339 p.
Dimensions
Height: 241 mm
Width: 160 mm
Thickness: 25 mm
Weight
711 gr
ISBN-13
978-0-7923-9364-1 (9780792393641)
DOI
10.1007/978-1-4615-3212-5
Schweitzer Classification
Other editions
Additional editions
Luciano Lavagno | Alberto L. Sangiovanni-Vincentelli
Algorithms for Synthesis and Testing of Asynchronous Circuits
Book
09/2012
Springer
€235.39
Shipment within 7-9 days
Content
1 Introduction.- 1.1 Motivation.- 1.2 Organization.- 2 Overview of The Design Methodology.- 2.1 Signal Transition Graphs.- 2.2 Signal Transition Graph Synthesis.- 2.3 The VMEbus Master Interface Protocol.- 2.4 A Signal Transition Graph Specification for the VMEbus Interface.- 2.5 The Circuit Implementation of the VMEbus Master Interface.- 3 Previous Work.- 3.1 Circuit Model Taxonomy.- 3.2 Definitions.- 3.3 The Huffman Model for Asynchronous Circuits.- 3.4 Micropipelines.- 3.5 Speed-independent Circuits.- 3.6 Delay-insensitive Circuits.- 3.7 Hazard Analysis in Asynchronous Circuits.- 3.8 Conclusion.- 4 The Signal Transition Graph Model.- 4.1 A Low-level Model for Asynchronous Systems.- 4.2 Modeling Asynchronous Logic Circuits.- 4.3 A High-level Behavioral Model for Asynchronous Systems.- 4.4 Classification of Models of Asynchronous Circuits.- 4.5 Signal Transition Graphs and Change Diagrams.- 4.6 Conclusion.- 5 The State Encoding Methodology.- 5.1 Overview of the State Encoding Methodology.- 5.2 From Signal Transition Graphs to Finite State Machines.- 5.3 Constrained Finite State Machine Minimization.- 5.4 State Signal Insertion.- 5.5 Experimental Results.- 6 The Synthesis Methodology.- 6.1 Hazard Analysis and Signal Transition Graphs.- 6.2 Circuit Implementation of the Next State Function.- 6.3 Static Hazard Detection in the Circuit Implementation.- 6.4 Hazard Elimination by Delay Padding.- 6.5 Dynamic Hazard Analysis.- 6.6 Experimental Results.- 7 The Design For Testability Methodology.- 7.1 Definitions and Notation.- 7.2 A Procedure Guaranteed to Generate an HFRPDFT Circuit.- 7.3 Heuristic Procedures to Improve HFRPDFT Testability.- 7.4 A Procedure Guaranteed to Generate an RGDFT Circuit.- 7.5 Design for Delay Testability Methodology.- 7.6 Experimental Results.- 8 Conclusions.- References.