
Verified Software. Theories, Tools and Experiments.
14th International Conference, VSTTE 2022, Trento, Italy, October 17-18, 2022, Revised Selected Papers
Springer (Publisher)
Published on 2. February 2023
Book
Paperback/Softback
VIII, 167 pages
978-3-031-25802-2 (ISBN)
Description
This book constitutes the refereed proceedings of the 14th International Conference on Verified Software. Theories, Tools and Experiments, VSTTE 2022 held in Trento, Italy, during October 17-18, 2022.
The 9 papers presented in this volume were carefully reviewed and selected from 20 submissions. The papers describe software verification efforts that involve collaboration, theory unification, tool integration, and formalized domain knowledge as well as novel experiments and case studies evaluating verification techniques and technologies.
More details
Series
Edition
1st ed. 2023
Language
English
Place of publication
Cham
Switzerland
Publishing group
Springer International Publishing
Target group
Professional and scholarly
Illustrations
195 s/w Abbildungen, 20 farbige Abbildungen
VIII, 167 p. 215 illus., 20 illus. in color.
Dimensions
Height: 235 mm
Width: 155 mm
Thickness: 11 mm
Weight
283 gr
ISBN-13
978-3-031-25802-2 (9783031258022)
DOI
10.1007/978-3-031-25803-9
Schweitzer Classification
Other editions
Additional editions

Akash Lal | Stefano Tonetta
Verified Software. Theories, Tools and Experiments.
14th International Conference, VSTTE 2022, Trento, Italy, October 17-18, 2022, Revised Selected Papers
E-Book
01/2023
Springer
€53.49
Available for download
Content
Compositional Safety LTL Synthesis.- Leroy and Blazy were right: their memory model soundness proof is automatable.- Shellac: a compiler synthesizer for concurrent programs.- A sequentialization procedure for fault-tolerant protocols.- Towards Practical Partial Order Reduction for High-Level Formalisms.- SMT-based Verification of Persistency Invariants of Px86 Programs.- A Formal Semantics for P-Code.- Separating Separation Logic - Modular Verification of Red-Black Trees.- Residual Runtime Verification via Reachability Analysis.