Microprocessors and Interfacing

PREFACE ; 1. MICROPROCESSORS-EVOLUTION AND INTRODUCTION ; 1.1 INTRODUCTION ; 1.2 EXPLANATION OF BASIC TERMS ; 1.3 MICROPROCESSORS AND MICROCONTROLLERS ; 1.4 MICROPROCESSOR-BASED SYSTEM ; 1.5 ORIGIN OF MICROPROCESSORS ; 1.5.1 FIRST GENERATION (1971-1973) ; 1.5.2 SECOND GENERATION (1974-1978) ; 1.5.3 THIRD GENERATION (1978-1980) ; 1.5.4 FOURTH GENERATION (1981-1995) ; 1.5.5 FIFTH GENERATION (1995-TILL DATE) ; 1.5.6 TIMELINE OF MICROPROCESSOR EVOLUTION ; 1.6 CLASSIFICATION OF MICROPROCESSORS ; 1.7 TYPES OF MEMORY ; 1.8 INPUT AND OUTPUT DEVICES ; 1.9 TECHNOLOGY IMPROVEMENTS ADAPTED TO MICROPROCESSORS AND COMPUTERS ; 1.10 ARCHITECTURE AND SIGNALS OF 8085 ; 1.11 INSTRUCTION SET OF 8085 ; 1.12 MEMORY AND I/O INTERFACING WITH 8085 ; 1.13 INTERRUPT STRUCTURE OF 8085 ; 2. METHODS OF DATA TRANSFER AND SERIAL TRANSFER PROTOCOLS ; 2.1 DATA TRANSFER MECHANISMS ; 2.2 MEMORY-MAPPED AND I/O-MAPPED DATA TRANSFER ; 2.3 PROGRAMMED DATA TRANSFER ; 2.4 DIRECT MEMORY ACCESS ; 2.5 PARALLEL DATA TRANSFER ; 2.5.1 PCI BUS ; 2.6 SERIAL DATA TRANSFER ; 2.6.1 INTRODUCTION TO RS-232 STANDARD ; 2.6.2 INTRODUCTION TO RS-485 STANDARD ; 2.6.3 GPIB/IEEE 488 STANDARDS ; 2.6.4 USB ; PART 1: INTEL 8086-16-BIT MICROPROCESSORS ; 3. INTEL 8086 MICROPROCESSOR ARCHITECTURE, FEATURES, AND SIGNALS ; 3.1 INTRODUCTION ; 3.2 ARCHITECTURE OF 8086 ; 3.2.1 EXECUTION UNIT ; 3.2.2 BUS INTERFACE UNIT ; 3.2.3 DIFFERENCES BETWEEN 8086 AND 8088 ; 3.3 ACCESSING MEMORY LOCATIONS ; 3.4 PIN DETAILS OF 8086 ; 3.4.1 FUNCTION OF PINS COMMON TO MINIMUM AND MAXIMUM MODES ; 3.4.2 FUNCTION OF PINS USED IN MINIMUM MODE ; 3.4.3 FUNCTION OF PINS USED IN MAXIMUM MODE ; 4. ADDRESSING MODES, INSTRUCTION SET, AND PROGRAMMING OF 8086 ; 4.1 ADDRESSING MODES IN 8086 ; 4.1.1 REGISTER ADDRESSING MODE ; 4.1.2 IMMEDIATE ADDRESSING MODE ; 4.1.3 DATA MEMORY ADDRESSING MODES ; 4.1.4 PROGRAM MEMORY ADDRESSING MODES ; 4.1.5 STACK MEMORY ADDRESSING MODE ; 4.2 SEGMENT OVERRIDE PREFIX ; 4.3 INSTRUCTION SET OF 8086 ; 4.3.1 DATA TRANSFER INSTRUCTIONS ; 4.3.2 ARITHMETIC INSTRUCTIONS ; 4.3.3 LOGICAL INSTRUCTIONS ; 4.3.4 FLAG MANIPULATION INSTRUCTIONS ; 4.3.5 CONTROL TRANSFER INSTRUCTIONS ; 4.3.6 SHIFT/ROTATE INSTRUCTIONS ; 4.3.7 STRING INSTRUCTIONS ; 4.3.8 MACHINE OR PROCESSOR CONTROL INSTRUCTIONS ; 4.4 8086 ASSEMBLY LANGUAGE PROGRAMMING ; 4.4.1 WRITING 8086 PROGRAMS USING LINE ASSEMBLER ; 4.4.2 8086 ASSEMBLER DIRECTIVES ; 4.4.3 WRITING ASSEMBLY LANGUAGE PROGRAMS USING MASM ; 4.5 PROGRAM DEVELOPMENT PROCESS ; 4.6 MODULAR PROGRAMMING ; 4.6.1 CALL INSTRUCTION: ; 4.6.2 RET INSTRUCTION ; 4.6.3 MACRO ; 4.6.3.1 ILLUSTRATIVE EXAMPLE ; 5. 8086 INTERRUPTS ; 5.1 INTRODUCTION ; 5.2 INTERRUPT TYPES IN 8086 ; 5.3 PROCESSING OF INTERRUPTS BY 8086 ; 5.4 DEDICATED INTERRUPT TYPES IN 8086 ; 5.4.1 TYPE 00H OR DIVIDE-BY-ZERO INTERRUPTS ; 5.4.2 TYPE 01H, SINGLE STEP, OR TRAP INTERRUPT ; 5.4.3 TYPE 02H OR NMI INTERRUPT ; 5.4.4 TYPE 03H OR ONE-BYTE INT INTERRUPT ; 5.4.5 TYPE 04H OR OVERFLOW INTERRUPT ; 5.5 SOFTWARE INTERRUPTS-TYPES 00H-FFH ; 5.6 INTR INTERRUPTS-TYPES 00H-FFH ; 5.7 PRIORITY AMONG 8086 INTERRUPTS ; 5.8 INTERRUPT SERVICE ROUTINES ; 5.9 BIOS INTERRUPTS OR FUNCTION CALLS ; 5.9.1 INT 10H ; 5.9.2 INT 11H ; 5.9.3 INT 12H ; 5.9.4 INT 13H ; 5.9.5 INT 14H ; 5.9.6 INT 15H ; 5.9.7 INT 16H ; 5.9.8 INT 17H ; 5.10. INTERRUPT HANDLERS ; 5.11 DOS SERVICES: INT 21H ; 5.11.1 EXAMPLE_1 ; 5.11.2 EXAMPLE_2 ; 5.12 SYSTEM CALLS: BIOS SERVICES ; 5.12.1 PRINT SCREEN SERVICE: INT 05H ; 5.12.2 VIDEO SERVICES: INT 10H ; 5.12.3 KEYBOARD SERVICES: INT 16H ; 5.12.3.1 EXAMPLE_1 ; 5.12.3.2 EXAMPLE_2 ; 5.12.4 PRINTER SERVICES: INT 17H ; 5.12.4.1 EXAMPLE_1 ; 5.12.4.2 EXAMPLE_2 ; 6. BASIC MEMORY AND I/O INTERFACING WITH 8086 ; 6.1 PHYSICAL MEMORY ORGANIZATION IN 8086 ; 6.2 FORMATION OF SYSTEM BUS ; 6.3 INTERFACING RAM AND EPROM CHIPS USING ONLY LOGIC GATES ; 6.4 INTERFACING RAM/EPROM CHIPS USING DECODER IC AND LOGIC GATES ; 6.5 I/O INTERFACING ; 6.5.1 I/O INSTRUCTIONS IN 8086 ; 6.5.2 I/O-MAPPED AND MEMORY-MAPPED I/O ; 6.6 INTERFACING 8-BIT INPUT DEVICE WITH 8086 ; 6.6.1 ASSIGNING 8-BIT ADDRESS TO 8-BIT INPUT DEVICE USING ADDRESS DECODER HAVING ONLY LOGIC GATES ; 6.6.2 ASSIGNING 8-BIT ADDRESS TO 8-BIT INPUT DEVICE USING ADDRESS DECODER IC 74LS138 ; 6.6.3 ASSIGNING 16-BIT ADDRESS TO 8-BIT DIP SWITCH USING ADDRESS DECODER HAVING ONLY LOGIC GATES ; 6.7 INTERFACING 8-BIT OUTPUT DEVICE WITH 8086 ; 6.8 INTERFACING 8-BIT AND 16-BIT I/O DEVICES OR PORTS WITH 8086 ; 7. FEATURES AND INTERFACING OF PROGRAMMABLE PERIPHERAL DEVICES WITH 8086 ; 7.1 INTEL 8255 PROGRAMMABLE PERIPHERAL INTERFACE ; 7.1.1 FEATURES OF 8255 ; 7.1.2 BLOCK DIAGRAM OF INTEL 8255 ; 7.1.3 OPERATING MODES AND CONTROL WORDS OF 8255 ; 7.1.4 CONFIGURING EXAMPLES ; 7.1.5 OTHER PROGRAMMABLE PERIPHERAL INTERFACE ICS -8155 AND 8755 ; 7.2 INTERFACING SWITCHES AND LEDS ; 7.3 INTERFACING SEVEN-SEGMENT DISPLAYS ; 7.4 TRAFFIC LIGHT CONTROL ; 7.5 INTERFACING ANALOG-TO-DIGITAL CONVERTERS ; 7.6 INTERFACING DIGITAL-TO-ANALOG CONVERTERS ; 7.6.1 SQUARE WAVE GENERATION ; 7.6.2 STAIRCASE WAVEFORM GENERATION ; 7.6.3 RAMP WAVEFORM GENERATION ; 7.6.4 WAVEFORM GENERATION USING STORED DATA ; 7.7 INTERFACING STEPPER MOTORS ; 7.8 INTERFACING INTELLIGENT LCDS ; 7.9 KEYBOARD AND DISPLAY INTERFACE IC 8279 ; 7.9.1 MATRIX KEYBOARD ; 7.9.2 MULTIPLEXED DISPLAY ; 7.9.3 FEATURES, BLOCK DIAGRAM, AND PIN DETAILS OF 8279 ; 7.9.4 PROGRAMMING OF 8279 ; 7.9.5 DISPLAY INTERFACE USING 8279 ; WITH 8086 ; 7.9.6 KEYBOARD INTERFACE USING 8279 WITH 8086 ; 7.10 INTEL TIMER IC 8253 ; 7.10.1 FEATURES OF IC 8253 ; 7.10.2 BLOCK DIAGRAM OF IC 8253 AND PIN DETAILS ; 7.10.3 OPERATING MODES AND CONTROL WORD OF IC 8253 ; 7.10.4 INTERFACING IC 8253 WITH 8086 ; 7.11 INTRODUCTION TO SERIAL COMMUNICATION ; 7.11.1 FEATURES AND DETAILS OF 8251 USART ; 7.11.2 CONTROL WORDS ; 7.11.3 INTERFACING 8251 WITH 8086 ; 7.12 8259 PROGRAMMABLE INTERRUPT CONTROLLER ; 7.12.1 FEATURES AND ARCHITECTURE OF 8259 ; 7.12.2 PIN DIAGRAM AND DETAILS OF 8259 ; 7.12.3 INITIALIZATION OF 8259 ; 7.12.4 OPERATION OF 8259 ; 7.12.5 INTERFACING 8259 WITH 8086 ; 7.13 8237 DMA CONTROLLER ; 7.13.1 FEATURES, PIN DETAILS, AND ARCHITECTURE OF 8237 ; 7.13.2 DMA INITIALIZATION AND OPERATION ; 7.13.3 OPERATION OF 8237 WITH 8086 ; 7.14 INTERFACING PRINTER WITH 8086 ; 7.15 INTERFACING CRT TERMINAL WITH 8086 ; 529 ; 8. MULTIPROCESSOR CONFIGURATION ; 8.1 INTRODUCTION ; 8.2 MULTIPROCESSOR SYSTEM-NEED AND ADVANTAGES ; 8.3 DIFFERENT CONFIGURATIONS OF MULTIPROCESSOR SYSTEM ; 8.3.1 COPROCESSOR AND CLOSELY-COUPLED CONFIGURATIONS ; 8.3.2 LOOSELY-COUPLED CONFIGURATION ; 8.4 BUS ARBITRATION IN LOOSELY-COUPLED MULTIPROCESSOR SYSTEM ; 8.4.1 DAISY CHAINING ; 8.4.2 POLLING ; 8.4.3 INDEPENDENT REQUESTING ; 8.5 INTERCONNECTION TOPOLOGIES IN A MULTIPROCESSOR SYSTEM ; 8.5.1 SHARED BUS ARCHITECTURE ; 8.5.2 MULTI-PORT MEMORY ; 8.5.3 LINKED INPUT/OUTPUT ; 8.5.4 CROSSBAR SWITCHING ; 8.6 PHYSICAL INTERCONNECTIONS BETWEEN PROCESSORS IN A MULTIPROCESSOR SYSTEM ; 8.6.1 STAR CONFIGURATION ; 8.6.2 RING OR LOOP CONFIGURATION ; 8.6.3 COMPLETELY-CONNECTED CONFIGURATION ; 8.6.4 REGULAR TOPOLOGY ; 8.6.5 IRREGULAR TOPOLOGY ; 8.7 OPERATING SYSTEM USED IN A MULTIPROCESSOR SYSTEM ; 8.8 TYPICAL MULTIPROCESSOR SYSTEM HAVING 8086 AND 8087 ; 8.8.1 ARCHITECTURE OF 8087 ; 8.8.2 PIN DETAILS OF 8087 ; 8.8.3 INTERCONNECTION OF 8087 WITH 8086 ; 8.8.4 DATA TYPES OF 8087 ; 8.9 TYPICAL MULTIPROCESSOR SYSTEM HAVING 8086 AND 8089 ; 8.9.1 PIN DETAILS OF 8089 ; 8.9.2 LOCAL AND REMOTE OPERATION OF 8089 ; 8.9.3 8089 (IOP) ARCHITECTURE ; 8.9.4 COMMUNICATION BETWEEN CPU (8086) AND IOP (8089) ; 9. 8086-BASED SYSTEMS ; 9.1 INTRODUCTION ; 9.2 8086 IN MINIMUM MODE CONFIGURATION ; 9.2.1 FORMATION OF SEPARATE ADDRESS BUS AND DATA BUS IN 8086 ; 9.2.2 FORMATION OF BUFFERED ADDRESS BUS AND DATA BUS IN 8086 ; 9.2.3 CONNECTION OF 8284A WITH 8086 ; 9.3 8086 IN MAXIMUM MODE CONFIGURATION ; 9.4 8086 SYSTEM BUS TIMINGS ; 9.4.1 TIMING DIAGRAMS FOR GENERAL BUS OPERATION IN MINIMUM MODE ; 9.4.2 TIMING DIAGRAMS FOR GENERAL BUS OPERATION IN MAXIMUM MODE ; 9.4.3 INTERRUPT ACKNOWLEDGEMENT (INTA) TIMING ; 9.4.4 BUS REQUEST AND BUS GRANT TIMING ; 9.5 DESIGN OF MINIMUM MODE 8086-BASED SYSTEM ; PART 2: INTEL 8051 MICROCONTROLLERS ; 10. INTRODUCTION TO 8051 MICROCONTROLLERS ; 10.1 INTRODUCTION ; 10.2 INTEL'S MCS-51 SERIES MICROCONTROLLERS ; 10.3 INTEL 8051 ARCHITECTURE ; 10.4 MEMORY ORGANIZATION ; 10.5 INTERNAL RAM STRUCTURE ; 10.5.1 SPECIAL FUNCTION REGISTERS ; 10.5.2 PROCESSOR STATUS WORD ; 10.6 POWER CONTROL IN 8051 ; 10.6.1 IDLE MODE ; 10.6.2 POWER DOWN MODE ; 10.7 STACK OPERATION ; 11. 8051 INSTRUCTION SET AND PROGRAMMING ; 11.1 INTRODUCTION ; 11.2 ADDRESSING MODES OF 8051 ; 11.2.1 IMMEDIATE ADDRESSING ; 11.2.2 REGISTER DIRECT ADDRESSING ; 11.2.3 MEMORY DIRECT ADDRESSING ; 11.2.4 MEMORY INDIRECT ADDRESSING ; 11.2.5 INDEXED ADDRESSING ; 11.3 INSTRUCTION SET OF 8051 ; 11.3.1 DATA TRANSFER INSTRUCTIONS ; 11.3.2 ARITHMETIC INSTRUCTIONS ; 11.3.3 LOGICAL INSTRUCTIONS ; 11.3.4 BRANCHING INSTRUCTIONS ; 11.3.5 BIT MANIPULATION INSTRUCTIONS ; 11.4 SOME ASSEMBLER DIRECTIVES ; 11.5 PROGRAMMING EXAMPLES USING 8051 INSTRUCTION SET ; 12. HARDWARE FEATURES OF 8051 ; 12.1 INTRODUCTION ; 12.2 PARALLEL PORTS IN 8051 ; 12.2.1 STRUCTURE OF PORT 1 ; 12.2.2 STRUCTURE OF PORTS 0 AND 2 ; 12.2.3 STRUCTURE OF PORT 3 ; 12.3 EXTERNAL MEMORY INTERFACING IN 8051 ; 12.3.1 PROGRAM MEMORY INTERFACING ; 12.3.2 DATA MEMORY INTERFACING ; 12.3.3 TIMING DIAGRAM FOR EXTERNAL PROGRAM AND DATA MEMORY ACCESS ; 12.4 8051 TIMERS ; 12.4.1 TIMER SFRS ; 12.4.2 TIMER OPERATING MODES ; 12.4.3 TIMER CONTROL AND OPERATION ; 12.4.4 USING TIMERS AS COUNTERS ; 12.4.5 PROGRAMMING EXAMPLES ; 12.5 8051 INTERRUPTS ; 12.5.1 INTERRUPT SOURCES AND INTERRUPT VECTOR ADDRESSES ; 12.5.2 ENABLING AND DISABLING OF INTERRUPTS ; 12.5.3 INTERRUPT PRIORITIES AND POLLING SEQUENCE ; 12.5.4 TIMING OF INTERRUPTS ; 12.5.5 PROGRAMMING EXAMPLES ; 12.6 8051 SERIAL PORTS ; 12.6.1 SERIAL PORT CONTROL SFRS ; 12.6.2 OPERATING MODES ; 12.6.3 PROGRAMMING SERIAL PORT ; 13. INTERFACE EXAMPLES ; 13.1 INTERFACING 8255 WITH 8051 ; 13.2 INTERFACING OF PUSH BUTTON SWITCHES AND LEDS ; 13.3 INTERFACING OF SEVEN-SEGMENT DISPLAYS ; 13.4 INTERFACING ADC CHIP ; 13.5 INTERFACING DAC CHIP ; 13.5.1 SQUARE WAVE GENERATION ; 13.5.2 STAIRCASE WAVE GENERATION ; 13.5.3 RAMP WAVE GENERATION ; 13.5.4 SINE WAVE GENERATION ; 13.6 INTERFACING MATRIX KEYPAD ; 13.7 INTERFACING STEPPER MOTOR WITH 8051 ; 13.8 INTERFACING LCD WITH 8051 ; 13.9 INTERFACING DC MOTORS/SERVOMOTORS ; 13.10 MICROCONTROLLER APPLICATION EXAMPLE-STOPWATCH ; 13.11 MICROCONTROLLER APPLICATION EXAMPLE-TRAFFIC LIGHT CONTROL ; 13.12 MICROCONTROLLER APPLICATION EXAMPLE-THERMOMETER ; 13.13 RTC INTERFACING USING I2C STANDARD ; 13.13.1 DETAILS OF I2C BUS ; 13.13.2 8051 SUBROUTINES USED TO IMPLEMENT I2C BUS ; 13.13.3 DS1307-SERIAL I2C REAL-TIME CLOCK IC ; 13.14 WASHING MACHINE CONTROL ; 13.15 ELEVATOR / LIFT INTERFACE ; PART 3: INTEL 8096-16-BIT MICROCONTROLLERS ; 14. OVERVIEW OF INTEL 8096 MICROCONTROLLERS ; 14.1 INTRODUCTION ; 14.2 FEATURES OF INTEL 8096 MICROCONTROLLER ; 14.3 FUNCTIONAL BLOCK DIAGRAM OF INTEL 8096 MICROCONTROLLER ; 14.3.1 CPU SECTION ; 14.3.2 8096 CPU BUSES ; 14.3.3 REGISTER ARITHMETIC AND LOGICAL UNIT ; 14.3.4 TEMPORARY REGISTER ; 14.3.5 REGISTER FILE ; 14.3.6 PROGRAM STATUS WORD ; 14.3.7 MEMORY CONTROLLER ; 14.3.8 INTERNAL TIMING ; 14.3.9 I/O SECTION ; 14.4 MEMORY STRUCTURE OF 8096 ; 14.5 POWER DOWN MODE OF CPU ; 15. 8096 INSTRUCTION SET AND PROGRAMMING ; 15.1 8096 OPERAND TYPES ; 15.2 ADDRESSING MODES ; 15.2.1 REGISTER DIRECT ADDRESSING ; 15.2.2 INDIRECT ADDRESSING ; 15.2.3 INDIRECT ADDRESSING WITH AUTO INCREMENT ; 15.2.4 IMMEDIATE ADDRESSING ; 15.2.5 SHORT-INDEXED ADDRESSING ; 15.2.6 LONG-INDEXED ADDRESSING ; 15.2.7 ZERO REGISTER ADDRESSING ; 15.2.8 STACK POINTER REGISTER ADDRESSING ; 15.3 CLASSIFICATION OF INSTRUCTIONS ; 15.3.1 DATA TRANSFER INSTRUCTIONS ; 15.3.2 ARITHMETIC AND LOGICAL INSTRUCTIONS ; 15.3.3 SHIFT/ROTATE INSTRUCTIONS ; 15.3.4 BRANCHING INSTRUCTIONS ; 15.4 COMPLETE 8096 INSTRUCTION SET ; 15.5 PROGRAMMING EXAMPLES USING 8096 INSTRUCTION SET ; 16. HARDWARE FEATURES OF 8096 ; 16.1 PARALLEL PORTS IN 8096 AND THEIR STRUCTURE ; 16.1.1 PORT 0 ; 16.1.2 PORT 1 ; 16.1.3 PORT 2 ; 16.1.4 PORT 3 AND PORT 4 ; 16.2 CONTROL AND STATUS REGISTERS ; 16.2.1 INPUT/OUTPUT CONTROL REGISTER 0 ; 16.2.2 INPUT/OUTPUT CONTROL REGISTER 1 ; 16.2.3 INPUT/OUTPUT STATUS REGISTER 0 ; 16.2.4 INPUT/OUTPUT STATUS REGISTER 1 ; 16.3 TIMERS ; 16.3.1 TIMER 1 ; 16.3.2 TIMER 2 ; 16.4 INTERRUPTS ; 16.4.1 INTERRUPT SOURCES ; 16.4.2 POLLING ROUTINE ; 16.4.3 VECTORED INTERRUPT ; 16.4.4 INTERRUPT CONTROL ; 16.4.5 INTERRUPT PENDING REGISTER ; 16.4.6 INTERRUPT MASK REGISTER ; 16.4.7 GLOBAL DISABLE ; 16.4.8 PROGRAM STATUS WORD (PSW) ; 16.5 SERIAL PORTS ; 16.5.1 OPERATING MODES OF SERIAL PORT ; 16.5.2 SERIAL PORT CONTROL/STATUS REGISTERS ; 16.5.3 DETERMINING BAUD RATE ; 16.5.4 PROGRAM FOR SERIAL PORT DATA RECEPTION ; 16.6 ANALOG-TO-DIGITAL CONVERTER ; 16.7 DIGITAL-TO-ANALOG CONVERTER ; 16.8 HIGH SPEED INPUT UNIT ; 16.8.1 HSI INTERRUPTS ; 16.8.2 PROGRAMMING HSI ; 16.9 HIGH SPEED OUTPUT UNIT ; 16.9.1 HSO STATUS ; 16.10 MEMORY EXPANSION ; 16.10.1 SINGLE CHIP MODE ; 16.10.2 EXPANDED MODE ; 16.10.3 CHOICE OF BUS WIDTH ; 16.10.4 BUS CONTROL ; 16.10.5 ROM/EPROM LOCK ; PART 4: ADVANCED TRENDS ; 17. MICROPROCESSOR SYSTEM DEVELOPMENTS AND RECENT TRENDS ; 17.1 INTRODUCTION ; 17.2 MICROCONTROLLER FEATURES AND DEVELOPMENTS ; 17.3 MICROPROCESSOR DEVELOPMENT SYSTEMS ; 17.3.1 IN-SYSTEM PROGRAMMING ; 17.3.2 DEBUGGER ; 17.3.3 EMULATOR ; 17.4 CROSS COMPILER FOR 8051 ; 17.5 PROGRAMMING 8051 IN C LANGUAGE ; 18. ADVANCED MICROPROCESSORS AND MICROCONTROLLERS ; 18.1 INTRODUCTION ; 18.2 80186 MICROPROCESSOR ; 18.2.1 ARCHITECTURE ; 18.2.2 INSTRUCTION SET OF 80186 ; 18.3 80286 MICROPROCESSOR ; 18.3.1 ARCHITECTURE ; 18.3.2 REGISTER ORGANIZATION AND REAL OR PROTECTED ADDRESSING IN 80286 ; 18.3.3 PRIVILEGE LEVELS IN PROTECTED MODE OF OPERATION ; 18.3.4 DESCRIPTOR CACHE OR PROGRAM-INVISIBLE REGISTERS ; 18.3.5 ACCESSING MEMORY USING GDT AND LDT ; 18.3.6 MULTITASKING IN 80286 ; 18.3.7 ADDRESSING MODES AND NEW INSTRUCTIONS IN 80286 ; 18.3.7 FLAG REGISTER ; 18.4 80386 MICROPROCESSOR ; 18.4.1 ARCHITECTURE OF 80386 ; 18.4.2 REGISTER ORGANIZATION IN 80386 ; 18.4.3 INSTRUCTION SET OF 80386 ; 18.4.4 ADDRESSING MEMORY IN PROTECTED MODE ; 18.4.5 PHYSICAL MEMORY ORGANIZATION IN 80386 ; 18.4.6 PAGING MECHANISM IN 80386 ; 18.5 80486 MICROPROCESSOR ; 18.6 PENTIUM MICROPROCESSOR ; 18.6.1 ARCHITECTURE OF PENTIUM ; 18.6.2 PROTECTED MODE OPERATION OF PENTIUM ; 18.6.3 ADDRESSING MODES IN PENTIUM ; 18.6.4 PAGING MECHANISM IN PENTIUM ; 18.7 OTHER VERSIONS OF PENTIUM ; 18.7.1 PENTIUM PRO PROCESSOR ; 18.7.2 PENTIUM II PROCESSOR ; 18.7.3 PENTIUM III PROCESSOR ; 18.7.4 PENTIUM 4 PROCESSOR ; 18.8 OPERATING MODES OF ADVANCE PROCESSORS ; 18.9 MODE TRANSITION ; 18.10 MEMORY MANAGEMENT IN PROTECTED MODE ; 18.11 SEGMENT DESCRIPTOR ; 18.12 PROTECTION: PURPOSE ; 18.12.1 TYPE CHECKING ; 18.12.2 ; LIMIT CHECKING/RESTRICTION OF ADDRESSABLE DOMAIN ; 18.12.3 PRIVILEGE LEVELS: ; 18.12.3.1 CHECK FOR DATA ACCESS IN DATA SEGMENT ; 18.12.3.2 CHECK FOR DATA ACCESS IN CODE SEGMENT ; 18.12.3.3 CHECK FOR CONTROL TRANSFERS ; 18.12.3.4 STACK SWITCHING ; 18.13 PROTECTED MODE INSTRUCTIONS ; 18.14 MULTITASKING ; 18.14.1 TIME SLICE SCHEDULING ; 18.14.2 BIT PERMISSION MAP ; 18.14.3 PRIORITY BASED SCHEDULING: ; 18.14.4 TASK SWITCHING IN PROTECTED MODE ; 18.14.4.1 TASK-STATE SEGMENT (TSS) ; 18.14.4.2 TSS DESCRIPTOR ; 18.14.4.3 TASK GATE DESCRIPTOR ; 18.14.4.4 CONTEXT/ TASK SWITCHING ; 19 EMBEDDED SYSTEMS ; 19.1 INTRODUCTION ; 19.1.1 CHARACTERISTICS OF EMBEDDED SYSTEMS ; 19.1.2 DESIGN METRIC ; 19.1.3 EVOLUTION OF EMBEDDED SYSTEM ; 19.1.4 DESIGN TECHNOLOGY ; 19.1.4.1 COMPILATION/SYNTHESIS ; 19.1.4.2 LIBRARIES/IP ; 19.1.4.3 TEST/VERIFICATION ; 19.2 CLASSIFICATION OF EMBEDDED SYSTEMS ; 19.3 EMBEDDED PROCESSOR ARCHITECTURES ; 19.3.1 RISC AND CISC ARCHITECTURES ; 19.3.2 SISD/SIMD ; 19.3.3 E200Z6 CORE ; 19.3.4 CELL MICROPROCESSOR ; 19.3.5 POWER PC ARCHITECTURE ; 19.3.6 OVERVIEW OF POWERPC ; 19.3.6.1 POWERPC FAMILY MEMBERS ; 19.3.6.2 FEATURES OF POWERPC 601 (MPC601) ; 19.3.7.PIC16F877 MICROCONTROLLER ; 19.3.7.1 FEATURES OF PIC16F877 ; 19.3.7.2 PIN DIAGRAM AND BLOCK DIAGRAM OF PIC16F877 ; 19.3.7.3 INSTRUCTION SET OF PIC16F877 ; 19.3.7.4 MEMORY ORGANIZATION IN PIC16F877 ; 19.3.7.5 ASSEMBLY LANGUAGE PROGRAMMING OF PIC16F877 ; 19.3.8 ARM MICROCONTROLLERS ; 19.3.8.1 ARM CORE ARCHITECTURE ; 19.3.8.2 BASIC ARM INSTRUCTIONS ; 19.3.8.3 VERSIONS OF ARM PROCESSORS AND FEATURE ; 19.4 SOFTWARE EMBEDDED IN TO SYSTEM ; 19.4.1 CO DESIGN ; 19.5 BUS ARCHITECTURES ; 19.5.1 PARALLEL BUS PROTOCOLS ; 19.5.2 SERIAL BUS PROTOCOLS ; 19.5.3 SERIAL WIRELESS PROTOCOLS ; 19.6 MEMORY ; 19.6.1 MEMORY TECHNOLOGIES ; 19.6.2 MEMORY HIERARCHY ; 19.6.3 MEMORY INTERFACING ; 19.7 I/O INTERFACING ; 19.8 SMART CARD DESIGN ; 19.8.1 VERTICAL (CONCURRENT) CODESIGN ; 19.8.2 HORIZONTAL (SERIAL) CODESIGN ; 19.8.3 SECURITY EXTENSION ; CHAPTER 20 HYBRID PROGRAMMING TECHNIQUES USING AMS & C/C++ ; 20.1 COMBINING ASSEMBLY LANGUAGE WITH C/C++ ; 20.2 CALLING CONVENTIONS ; 20.2.1 CDECL CALLING CONVENTION ; 20.2.2 STDCALL CALLING CONVENTION ; 20.2.3 FASTCALL CALLING CONVENTION ; 20.3 PASSING PARAMETER TECHNIQUES ; 20.4 TECHNIQUES FOR 16 BIT ALP MICROSOFT C/C++ FOR DOS. ; 20.4.1 INLINE ASSEMBLY ; 20.4.2 LINKED ASSEMBLY ; 20.5 USING ALP WITH C/C++ FOR 32-BIT APPLICATIONS ; 20.6 32-BIT WINDOWS PROGRAMMING ; 20.6.1 CONSOL FUNCTIONS ; 20.6.2 WIN32 APPLICATION PROGRAMMING INTERFACE (API). ; 20.7 PROGRAM DEVELOPMENT METHODS ; 20.7.1 GRAPHICAL USER INTERFACE ; 20.7.2 CREATING THE HYBRID _PRJ PROJECT ( MSVC6.0) ; 20.7.3 CREATING THE HYBRID _PRJ PROJECT (USING MICROSOFT VISUAL STUDIO) ; APPENDIX A: 8085 INSTRUCTION SET ; APPENDIX B: 8051 INSTRUCTION SET ; APPENDIX C: 8086 INSTRUCTION SET ; APPENDIX D: 8096 INSTRUCTION SET ; APPENDIX E: CASE STUDIES ; APPENDIX F: MULTIPLE CHOICE QUESTIONS ON 8085, 8086 AND 8051 ; BIBLIOGRAPHY