Machine Learning Techniques for VLSI Chip Design
1st Edition
Published on 18. July 2023
Book
Hardback
240 pages
978-1-119-91039-8 (ISBN)
Description
MACHINE LEARNING TECHNIQUES FOR VLSI CHIP DESIGN This cutting-edge new volume covers the hardware architecture implementation, the software implementation approach, the efficient hardware of machine learning applications with FPGA or CMOS circuits, and many other aspects and applications of machine learning techniques for VLSI chip design.
Artificial intelligence (AI) and machine learning (ML) have, or will have, an impact on almost every aspect of our lives and every device that we own. AI has benefitted every industry in terms of computational speeds, accurate decision prediction, efficient machine learning (ML), and deep learning (DL) algorithms. The VLSI industry uses the electronic design automation tool (EDA), and the integration with ML helps in reducing design time and cost of production. Finding defects, bugs, and hardware Trojans in the design with ML or DL can save losses during production. Constraints to ML-DL arise when having to deal with a large set of training datasets. This book covers the learning algorithm for floor planning, routing, mask fabrication, and implementation of the computational architecture for ML-DL.
The future aspect of the ML-DL algorithm is to be available in the format of an integrated circuit (IC). A user can upgrade to the new algorithm by replacing an IC. This new book mainly deals with the adaption of computation blocks like hardware accelerators and novel nano-material for them based upon their application and to create a smart solution. This exciting new volume is an invaluable reference for beginners as well as engineers, scientists, researchers, and other professionals working in the area of VLSI architecture development.
Artificial intelligence (AI) and machine learning (ML) have, or will have, an impact on almost every aspect of our lives and every device that we own. AI has benefitted every industry in terms of computational speeds, accurate decision prediction, efficient machine learning (ML), and deep learning (DL) algorithms. The VLSI industry uses the electronic design automation tool (EDA), and the integration with ML helps in reducing design time and cost of production. Finding defects, bugs, and hardware Trojans in the design with ML or DL can save losses during production. Constraints to ML-DL arise when having to deal with a large set of training datasets. This book covers the learning algorithm for floor planning, routing, mask fabrication, and implementation of the computational architecture for ML-DL.
The future aspect of the ML-DL algorithm is to be available in the format of an integrated circuit (IC). A user can upgrade to the new algorithm by replacing an IC. This new book mainly deals with the adaption of computation blocks like hardware accelerators and novel nano-material for them based upon their application and to create a smart solution. This exciting new volume is an invaluable reference for beginners as well as engineers, scientists, researchers, and other professionals working in the area of VLSI architecture development.
More details
Language
English
Place of publication
United States
Publishing group
John Wiley & Sons Inc
Target group
Professional and scholarly
Product notice
sewn/stitched
Cloth over boards
Weight
597 gr
ISBN-13
978-1-119-91039-8 (9781119910398)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Other editions
Additional editions
Abhishek Kumar | Suman Lata Tripathi | K. Srinivasa Rao
Machine Learning Techniques for VLSI Chip Design
E-Book
06/2023
1st Edition
Wiley
€177.99
Available for download
Abhishek Kumar | Suman Lata Tripathi | K. Srinivasa Rao
Machine Learning Techniques for VLSI Chip Design
E-Book
06/2023
1st Edition
Wiley
€177.99
Available for download
Persons
Abhishek Kumar, PhD, is an associate professor at and obtained his PhD in the area of VLSI design for low power and secured architecture from Lovely Professional University, India. With over 11 years of academic experience, he has published more than 30 research papers and proceedings in scholarly journals. He has also published nine book chapters and one authored book. He has worked as a reviewer and program committee member and editorial board member for academic and scholarly conferences and journals, and he has 11 patents to his credit.
Suman Lata Tripathi, PhD, is a professor at Lovely Professional University with more than 21 years of experience in academics. She has published more than 103 research papers in refereed journals and conferences. She has organized several workshops, summer internships, and expert lectures for students, and she has worked as a session chair, conference steering committee member, editorial board member, and reviewer for IEEE journals and conferences. She has published three books and currently has multiple volumes scheduled for publication from Wiley-Scrivener.
K. Srinivasa Rao, PhD, is a professor and Head of Microelectronics Research Group, Department of Electronics and Communication Engineering at the Koneru Lakshmaiah Education Foundation, India. He has earned multiple awards for his scholarship and has published more than 150 papers in scientific journals and presented more than 55 papers at scientific conferences around the world.
Suman Lata Tripathi, PhD, is a professor at Lovely Professional University with more than 21 years of experience in academics. She has published more than 103 research papers in refereed journals and conferences. She has organized several workshops, summer internships, and expert lectures for students, and she has worked as a session chair, conference steering committee member, editorial board member, and reviewer for IEEE journals and conferences. She has published three books and currently has multiple volumes scheduled for publication from Wiley-Scrivener.
K. Srinivasa Rao, PhD, is a professor and Head of Microelectronics Research Group, Department of Electronics and Communication Engineering at the Koneru Lakshmaiah Education Foundation, India. He has earned multiple awards for his scholarship and has published more than 150 papers in scientific journals and presented more than 55 papers at scientific conferences around the world.
Content
List of Contributors xiii
Preface xix
1 Applications of VLSI Design in Artificial Intelligence and Machine Learning 1
Imran Ullah Khan, Nupur Mittal and Mohd. Amir Ansari
1.1 Introduction 2
1.2 Artificial Intelligence 4
1.3 Artificial Intelligence & VLSI (AI and VLSI) 4
1.4 Applications of AI 4
1.5 Machine Learning 5
1.6 Applications of ml 6
1.6.1 Role of ML in Manufacturing Process 6
1.6.2 Reducing Maintenance Costs and Improving Reliability 6
1.6.3 Enhancing New Design 7
1.7 Role of ML in Mask Synthesis 7
1.8 Applications in Physical Design 8
1.8.1 Lithography Hotspot Detection 9
1.8.2 Pattern Matching Approach 9
1.9 Improving Analysis Correlation 10
1.10 Role of ML in Data Path Placement 12
1.11 Role of ML on Route Ability Prediction 12
1.12 Conclusion 13
References 14
2 Design of an Accelerated Squarer Architecture Based on Yavadunam Sutra for Machine Learning 19
A.V. Ananthalakshmi, P. Divyaparameswari and P. Kanimozhi
2.1 Introduction 20
2.2 Methods and Methodology 21
2.2.1 Design of an n-Bit Squaring Circuit Based on (n-1)-Bit Squaring Circuit Architecture 22
2.2.1.1 Architecture for Case 1: A < B 22
2.2.1.2 Architecture for Case 2: A > B 24
2.2.1.3 Architecture for Case 3: A = B 24
2.3 Results and Discussion 25
2.4 Conclusion 29
References 30
3 Machine Learning-Based VLSI Test and Verification 33
Jyoti Kandpal
3.1 Introduction 33
3.2 The VLSI Testing Process 35
3.2.1 Off-Chip Testing 35
3.2.2 On-Chip Testing 35
3.2.3 Combinational Circuit Testing 36
3.2.3.1 Fault Model 36
3.2.3.2 Path Sensitizing 36
3.2.4 Sequential Circuit Testing 36
3.2.4.1 Scan Path Test 36
3.2.4.2 Built-In-Self Test (BIST) 36
3.2.4.3 Boundary Scan Test (BST) 37
3.2.5 The Advantages of VLSI Testing 37
3.3 Machine Learning's Advantages in VLSI Design 38
3.3.1 Ease in the Verification Process 38
3.3.2 Time-Saving 38
3.3.3 3Ps (Power, Performance, Price) 38
3.4 Electronic Design Automation (EDA) 39
3.4.1 System-Level Design 40
3.4.2 Logic Synthesis and Physical Design 42
3.4.3 Test, Diagnosis, and Validation 43
3.5 Verification 44
3.6 Challenges 47
3.7 Conclusion 47
References 48
4 IoT-Based Smart Home Security Alert System for Continuous Supervision 51
Rajeswari, N. Vinod Kumar, K. M. Suresh, N. Sai Kumar and K. Girija Sravani
4.1 Introduction 52
4.2 Literature Survey 53
4.3 Results and Discussions 54
4.3.1 Raspberry Pi-3 B+Module 54
4.3.2 Pi Camera 56
4.3.3 Relay 56
4.3.4 Power Source 56
4.3.5 Sensors 56
4.3.5.1 IR & Ultrasonic Sensor 56
4.3.5.2 Gas Sensor 56
4.3.5.3 Fire Sensor 57
4.3.5.4 GSM Module 57
4.3.5.5 Buzzer 57
4.3.5.6 Cloud 57
4.3.5.7 Mobile 57
4.4 Conclusions 62
References 62
5 A Detailed Roadmap from Conventional-MOSFET to Nanowire-MOSFET 65
P. Kiran Kumar, B. Balaji, M. Suman, P. Syam Sundar, E. Padmaja and K. Girija Sravani
5.1 Introduction 66
5.2 Scaling Challenges Beyond 100nm Node 67
5.3 Alternate Concepts in MOFSETs 69
5.4 Thin-Body Field-Effect Transistors 70
5.4.1 Single-Gate Ultrathin-Body Field-Effect Transistor 71
5.4.2 Multiple-Gate Ultrathin-Body Field-Effect Transistor 73
5.5 Fin-FET Devices 74
5.6 GAA Nanowire-MOSFETS 77
5.7 Conclusion 86
References 86
6 Gate All Around MOSFETs-A Futuristic Approach 95
Ritu Yadav and Kiran Ahuja
6.1 Introduction 95
6.1.1 Semiconductor Technology: History 96
6.2 Importance of Scaling in CMOS Technology 98
6.2.1 Scaling Rules 99
6.2.2 The End of Planar Scaling 100
6.2.3 Enhance Power Efficiency 101
6.2.4 Scaling Challenges 102
6.2.4.1 Poly Silicon Depletion Effect 102
6.2.4.2 Quantum Effect 103
6.2.4.3 Gate Tunneling 103
6.2.5 Horizontal Scaling Challenges 103
6.2.5.1 Threshold Voltage Roll-Off 103
6.2.5.2 Drain Induce Barrier Lowering (DIBL) 103
6.2.5.3 Trap Charge Carrier 104
6.2.5.4 Mobility Degradation 104
6.3 Remedies of Scaling Challenges 104
6.3.1 By Channel Engineering (Horizontal) 104
6.3.1.1 Shallow S/D Junction 105
6.3.1.2 Multi-Material Gate 105
6.3.2 By Gate Engineering (Vertical) 105
6.3.2.1 High-K Dielectric 105
6.3.2.2 Metal Gate 105
6.3.2.3 Multiple Gate 105
6.4 Role of High-K in CMOS Miniaturization 106
6.5 Current Mosfet Technologies 108
6.6 Conclusion 108
References 109
7 Investigation of Diabetic Retinopathy Level Based on Convolution Neural Network Using Fundus Images 113
K. Sasi Bhushan, U. Preethi, P. Naga Sai Navya, R. Abhilash, T. Pavan and K. Girija Sravani
7.1 Introduction 114
7.2 The Proposed Methodology 115
7.3 Dataset Description and Feature Extraction 116
7.3.1 Depiction of Datasets 116
7.3.2 Preprocessing 116
7.3.3 Detection of Blood Vessels 117
7.3.4 Microaneurysm Detection 118
7.4 Results and Discussions 120
7.5 Conclusions 123
References 123
8 Anti-Theft Technology of Museum Cultural Relics Using RFID Technology 127
B. Ramesh Reddy, K. Bhargav Manikanta, P.V.V.N.S. Jaya Sai, R. Mohan Chandra, M. Greeshma Vyas and K. Girija Sravani
8.1 Introduction 128
8.2 Literature Survey 128
8.3 Software Implementation 129
8.4 Components 130
8.4.1 Arduino UNO 130
8.4.2 EM18 Reader Module 130
8.4.3 RFID Tag 131
8.4.4 LCD Display 131
8.4.5 Sensors 132
8.4.5.1 Fire Sensor 132
8.4.5.2 IR Sensor 132
8.4.6 Relay 133
8.5 Working Principle 134
8.5.1 Working Principle 134
8.6 Results and Discussions 135
8.7 Conclusions 137
References 138
9 Smart Irrigation System Using Machine Learning Techniques 139
B. V. Anil Sai Kumar, Suryavamsham Prem Kumar, Konduru Jaswanth, Kola Vishnu and Abhishek Kumar
9.1 Introduction 139
9.2 Hardware Module 141
9.2.1 Soil Moisture Sensor 141
9.2.2 LM35-Temperature Sensor 143
9.2.3 POT Resistor 143
9.2.4 BC-547 Transistor 143
9.2.5 Sounder 144
9.2.6 LCD 16x2 145
9.2.7 Relay 145
9.2.8 Push Button 146
9.2.9 Led 146
9.2.10 Motor 147
9.3 Software Module 148
9.3.1 Proteus Tool 148
9.3.2 Arduino Based Prototyping 149
9.4 Machine Learning (Ml) Into Irrigation 155
9.5 Conclusion 158
References 158
10 Design of Smart Wheelchair with Health Monitoring System 161
Narendra Babu Alur, Kurapati Poorna Durga, Boddu Ganesh, Manda Devakaruna, Lakkimsetti Nandini, A. Praneetha, T. Satyanarayana and K. Girija Sravani
10.1 Introduction 162
10.2 Proposed Methodology 163
10.3 The Proposed System 164
10.4 Results and Discussions 168
10.5 Conclusions 169
References 169
11 Design and Analysis of Anti-Poaching Alert System for Red Sandalwood Safety 171
K. Rani Rudrama, Mounika Ramala, Poorna sasank Galaparti, Manikanta Chary Darla, Siva Sai Prasad Loya and K. Srinivasa Rao
11.1 Introduction 172
11.2 Various Existing Proposed Anti-Poaching Systems 173
11.3 System Framework and Construction 174
11.4 Results and Discussions 176
11.5 Conclusion and Future Scope 182
References 182
12 Tumor Detection Using Morphological Image Segmentation with DSP Processor TMS320C 6748 185
T. Anil Raju, K. Srihari Reddy, Sk. Arifulla Rabbani, G. Suresh, K. Saikumar Reddy and K. Girija Sravani
12.1 Introduction 186
12.2 Image Processing 186
12.2.1 Image Acquisition 186
12.2.2 Image Segmentation Method 186
12.3 TMS320C6748 DSP Processor 187
12.4 Code Composer Studio 188
12.5 Morphological Image Segmentation 188
12.5.1 Optimization 190
12.6 Results and Discussions 192
12.7 Conclusions 193
References 193
13 Design Challenges for Machine/Deep Learning Algorithms 195
Rajesh C. Dharmik and Bhushan U. Bawankar
13.1 Introduction 196
13.2 Design Challenges of Machine Learning 197
13.2.1 Data of Low Quality 197
13.2.2 Training Data Underfitting 197
13.2.3 Training Data Overfitting 198
13.2.4 Insufficient Training Data 198
13.2.5 Uncommon Training Data 199
13.2.6 Machine Learning Is a Time-Consuming Process 199
13.2.7 Unwanted Features 200
13.2.8 Implementation is Taking Longer Than Expected 200
13.2.9 Flaws When Data Grows 200
13.2.10 The Model's Offline Learning and Deployment 200
13.2.11 Bad Recommendations 201
13.2.12 Abuse of Talent 201
13.2.13 Implementation 201
13.2.14 Assumption are Made in the Wrong Way 202
13.2.15 Infrastructure Deficiency 202
13.2.16 When Data Grows, Algorithms Become Obsolete 202
13.2.17 Skilled Resources are Not Available 203
13.2.18 Separation of Customers 203
13.2.19 Complexity 203
13.2.20 Results Take Time 203
13.2.21 Maintenance 204
13.2.22 Drift in Ideas 204
13.2.23 Bias in Data 204
13.2.24 Error Probability 204
13.2.25 Inability to Explain 204
13.3 Commonly Used Algorithms in Machine Learning 205
13.3.1 Algorithms for Supervised Learning 205
13.3.2 Algorithms for Unsupervised Learning 206
13.3.3 Algorithm for Reinforcement Learning 206
13.4 Applications of Machine Learning 207
13.4.1 Image Recognition 207
13.4.2 Speech Recognition 207
13.4.3 Traffic Prediction 207
13.4.4 Product Recommendations 208
13.4.5 Email Spam and Malware Filtering 208
13.5 Conclusion 208
References 208
About the Editors 211
Index 213
Preface xix
1 Applications of VLSI Design in Artificial Intelligence and Machine Learning 1
Imran Ullah Khan, Nupur Mittal and Mohd. Amir Ansari
1.1 Introduction 2
1.2 Artificial Intelligence 4
1.3 Artificial Intelligence & VLSI (AI and VLSI) 4
1.4 Applications of AI 4
1.5 Machine Learning 5
1.6 Applications of ml 6
1.6.1 Role of ML in Manufacturing Process 6
1.6.2 Reducing Maintenance Costs and Improving Reliability 6
1.6.3 Enhancing New Design 7
1.7 Role of ML in Mask Synthesis 7
1.8 Applications in Physical Design 8
1.8.1 Lithography Hotspot Detection 9
1.8.2 Pattern Matching Approach 9
1.9 Improving Analysis Correlation 10
1.10 Role of ML in Data Path Placement 12
1.11 Role of ML on Route Ability Prediction 12
1.12 Conclusion 13
References 14
2 Design of an Accelerated Squarer Architecture Based on Yavadunam Sutra for Machine Learning 19
A.V. Ananthalakshmi, P. Divyaparameswari and P. Kanimozhi
2.1 Introduction 20
2.2 Methods and Methodology 21
2.2.1 Design of an n-Bit Squaring Circuit Based on (n-1)-Bit Squaring Circuit Architecture 22
2.2.1.1 Architecture for Case 1: A < B 22
2.2.1.2 Architecture for Case 2: A > B 24
2.2.1.3 Architecture for Case 3: A = B 24
2.3 Results and Discussion 25
2.4 Conclusion 29
References 30
3 Machine Learning-Based VLSI Test and Verification 33
Jyoti Kandpal
3.1 Introduction 33
3.2 The VLSI Testing Process 35
3.2.1 Off-Chip Testing 35
3.2.2 On-Chip Testing 35
3.2.3 Combinational Circuit Testing 36
3.2.3.1 Fault Model 36
3.2.3.2 Path Sensitizing 36
3.2.4 Sequential Circuit Testing 36
3.2.4.1 Scan Path Test 36
3.2.4.2 Built-In-Self Test (BIST) 36
3.2.4.3 Boundary Scan Test (BST) 37
3.2.5 The Advantages of VLSI Testing 37
3.3 Machine Learning's Advantages in VLSI Design 38
3.3.1 Ease in the Verification Process 38
3.3.2 Time-Saving 38
3.3.3 3Ps (Power, Performance, Price) 38
3.4 Electronic Design Automation (EDA) 39
3.4.1 System-Level Design 40
3.4.2 Logic Synthesis and Physical Design 42
3.4.3 Test, Diagnosis, and Validation 43
3.5 Verification 44
3.6 Challenges 47
3.7 Conclusion 47
References 48
4 IoT-Based Smart Home Security Alert System for Continuous Supervision 51
Rajeswari, N. Vinod Kumar, K. M. Suresh, N. Sai Kumar and K. Girija Sravani
4.1 Introduction 52
4.2 Literature Survey 53
4.3 Results and Discussions 54
4.3.1 Raspberry Pi-3 B+Module 54
4.3.2 Pi Camera 56
4.3.3 Relay 56
4.3.4 Power Source 56
4.3.5 Sensors 56
4.3.5.1 IR & Ultrasonic Sensor 56
4.3.5.2 Gas Sensor 56
4.3.5.3 Fire Sensor 57
4.3.5.4 GSM Module 57
4.3.5.5 Buzzer 57
4.3.5.6 Cloud 57
4.3.5.7 Mobile 57
4.4 Conclusions 62
References 62
5 A Detailed Roadmap from Conventional-MOSFET to Nanowire-MOSFET 65
P. Kiran Kumar, B. Balaji, M. Suman, P. Syam Sundar, E. Padmaja and K. Girija Sravani
5.1 Introduction 66
5.2 Scaling Challenges Beyond 100nm Node 67
5.3 Alternate Concepts in MOFSETs 69
5.4 Thin-Body Field-Effect Transistors 70
5.4.1 Single-Gate Ultrathin-Body Field-Effect Transistor 71
5.4.2 Multiple-Gate Ultrathin-Body Field-Effect Transistor 73
5.5 Fin-FET Devices 74
5.6 GAA Nanowire-MOSFETS 77
5.7 Conclusion 86
References 86
6 Gate All Around MOSFETs-A Futuristic Approach 95
Ritu Yadav and Kiran Ahuja
6.1 Introduction 95
6.1.1 Semiconductor Technology: History 96
6.2 Importance of Scaling in CMOS Technology 98
6.2.1 Scaling Rules 99
6.2.2 The End of Planar Scaling 100
6.2.3 Enhance Power Efficiency 101
6.2.4 Scaling Challenges 102
6.2.4.1 Poly Silicon Depletion Effect 102
6.2.4.2 Quantum Effect 103
6.2.4.3 Gate Tunneling 103
6.2.5 Horizontal Scaling Challenges 103
6.2.5.1 Threshold Voltage Roll-Off 103
6.2.5.2 Drain Induce Barrier Lowering (DIBL) 103
6.2.5.3 Trap Charge Carrier 104
6.2.5.4 Mobility Degradation 104
6.3 Remedies of Scaling Challenges 104
6.3.1 By Channel Engineering (Horizontal) 104
6.3.1.1 Shallow S/D Junction 105
6.3.1.2 Multi-Material Gate 105
6.3.2 By Gate Engineering (Vertical) 105
6.3.2.1 High-K Dielectric 105
6.3.2.2 Metal Gate 105
6.3.2.3 Multiple Gate 105
6.4 Role of High-K in CMOS Miniaturization 106
6.5 Current Mosfet Technologies 108
6.6 Conclusion 108
References 109
7 Investigation of Diabetic Retinopathy Level Based on Convolution Neural Network Using Fundus Images 113
K. Sasi Bhushan, U. Preethi, P. Naga Sai Navya, R. Abhilash, T. Pavan and K. Girija Sravani
7.1 Introduction 114
7.2 The Proposed Methodology 115
7.3 Dataset Description and Feature Extraction 116
7.3.1 Depiction of Datasets 116
7.3.2 Preprocessing 116
7.3.3 Detection of Blood Vessels 117
7.3.4 Microaneurysm Detection 118
7.4 Results and Discussions 120
7.5 Conclusions 123
References 123
8 Anti-Theft Technology of Museum Cultural Relics Using RFID Technology 127
B. Ramesh Reddy, K. Bhargav Manikanta, P.V.V.N.S. Jaya Sai, R. Mohan Chandra, M. Greeshma Vyas and K. Girija Sravani
8.1 Introduction 128
8.2 Literature Survey 128
8.3 Software Implementation 129
8.4 Components 130
8.4.1 Arduino UNO 130
8.4.2 EM18 Reader Module 130
8.4.3 RFID Tag 131
8.4.4 LCD Display 131
8.4.5 Sensors 132
8.4.5.1 Fire Sensor 132
8.4.5.2 IR Sensor 132
8.4.6 Relay 133
8.5 Working Principle 134
8.5.1 Working Principle 134
8.6 Results and Discussions 135
8.7 Conclusions 137
References 138
9 Smart Irrigation System Using Machine Learning Techniques 139
B. V. Anil Sai Kumar, Suryavamsham Prem Kumar, Konduru Jaswanth, Kola Vishnu and Abhishek Kumar
9.1 Introduction 139
9.2 Hardware Module 141
9.2.1 Soil Moisture Sensor 141
9.2.2 LM35-Temperature Sensor 143
9.2.3 POT Resistor 143
9.2.4 BC-547 Transistor 143
9.2.5 Sounder 144
9.2.6 LCD 16x2 145
9.2.7 Relay 145
9.2.8 Push Button 146
9.2.9 Led 146
9.2.10 Motor 147
9.3 Software Module 148
9.3.1 Proteus Tool 148
9.3.2 Arduino Based Prototyping 149
9.4 Machine Learning (Ml) Into Irrigation 155
9.5 Conclusion 158
References 158
10 Design of Smart Wheelchair with Health Monitoring System 161
Narendra Babu Alur, Kurapati Poorna Durga, Boddu Ganesh, Manda Devakaruna, Lakkimsetti Nandini, A. Praneetha, T. Satyanarayana and K. Girija Sravani
10.1 Introduction 162
10.2 Proposed Methodology 163
10.3 The Proposed System 164
10.4 Results and Discussions 168
10.5 Conclusions 169
References 169
11 Design and Analysis of Anti-Poaching Alert System for Red Sandalwood Safety 171
K. Rani Rudrama, Mounika Ramala, Poorna sasank Galaparti, Manikanta Chary Darla, Siva Sai Prasad Loya and K. Srinivasa Rao
11.1 Introduction 172
11.2 Various Existing Proposed Anti-Poaching Systems 173
11.3 System Framework and Construction 174
11.4 Results and Discussions 176
11.5 Conclusion and Future Scope 182
References 182
12 Tumor Detection Using Morphological Image Segmentation with DSP Processor TMS320C 6748 185
T. Anil Raju, K. Srihari Reddy, Sk. Arifulla Rabbani, G. Suresh, K. Saikumar Reddy and K. Girija Sravani
12.1 Introduction 186
12.2 Image Processing 186
12.2.1 Image Acquisition 186
12.2.2 Image Segmentation Method 186
12.3 TMS320C6748 DSP Processor 187
12.4 Code Composer Studio 188
12.5 Morphological Image Segmentation 188
12.5.1 Optimization 190
12.6 Results and Discussions 192
12.7 Conclusions 193
References 193
13 Design Challenges for Machine/Deep Learning Algorithms 195
Rajesh C. Dharmik and Bhushan U. Bawankar
13.1 Introduction 196
13.2 Design Challenges of Machine Learning 197
13.2.1 Data of Low Quality 197
13.2.2 Training Data Underfitting 197
13.2.3 Training Data Overfitting 198
13.2.4 Insufficient Training Data 198
13.2.5 Uncommon Training Data 199
13.2.6 Machine Learning Is a Time-Consuming Process 199
13.2.7 Unwanted Features 200
13.2.8 Implementation is Taking Longer Than Expected 200
13.2.9 Flaws When Data Grows 200
13.2.10 The Model's Offline Learning and Deployment 200
13.2.11 Bad Recommendations 201
13.2.12 Abuse of Talent 201
13.2.13 Implementation 201
13.2.14 Assumption are Made in the Wrong Way 202
13.2.15 Infrastructure Deficiency 202
13.2.16 When Data Grows, Algorithms Become Obsolete 202
13.2.17 Skilled Resources are Not Available 203
13.2.18 Separation of Customers 203
13.2.19 Complexity 203
13.2.20 Results Take Time 203
13.2.21 Maintenance 204
13.2.22 Drift in Ideas 204
13.2.23 Bias in Data 204
13.2.24 Error Probability 204
13.2.25 Inability to Explain 204
13.3 Commonly Used Algorithms in Machine Learning 205
13.3.1 Algorithms for Supervised Learning 205
13.3.2 Algorithms for Unsupervised Learning 206
13.3.3 Algorithm for Reinforcement Learning 206
13.4 Applications of Machine Learning 207
13.4.1 Image Recognition 207
13.4.2 Speech Recognition 207
13.4.3 Traffic Prediction 207
13.4.4 Product Recommendations 208
13.4.5 Email Spam and Malware Filtering 208
13.5 Conclusion 208
References 208
About the Editors 211
Index 213