Design and Architecture for Signal and Image Processing

.- Reconfigurable Computing and Design Tools .

.- A Framework for Automated Integration of High-Level Simulators in RISC-V SoCs.

.- An Open-Source Framework Bridging System-Level Measurements and Circuit-Level Energy Consumption and Latency Characteristics.

.- MultiGRA: Expanding the CGRA Design Space with a Mixed- Granularity Approach.

.- Resource-Guided FPGA Floorplanning via Quad-Tree-Based NLP Optimization.

.- Sigma Delta DACs for Low Latency High Sampling Rate Audio on an FPGA.

.- AI Accelerators, Architectures and Benchmarking .

.- Automated Design of CNN-based Image Classifiers for Hailo-8L Accelerator.

.- Benchmarking Deep Learning Convolutions on Energy-constrained CPUs.

.- C3M-ViT: A Configurable Matrix Multiplication Module for Energy-Efficient Vision Transformer Accelerator.

.- Comparative Benchmark of Scaled-YOLOv4 on Graphcore IPU and NVIDIA GPU.

.- FPGA-Based Anomaly Detection for Medical IoT: Trade-Offs between hls4ml and FINN.

.- Training for Mixed-Precision Integer Weights, Activations and Embeddings in BERT.

.- Secure and Dependable Embedded Systems .

.- ARMOR : Accelerator Runtime Monitoring and cOntrolled identity enfoRcement.

.- BERT-Inspired HT Localization on FPGA AI Accelerators.

.- Fault Injection Attacks in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI.

.- UAVLnQ: An Architecture for Security Analysis of Cyber-Physical Network Behavior in UAV Swarms.