Cryptographic Hardware and Embedded Systems - CHES 2000
Second International Workshop Worcester, MA, USA, August 17-18, 2000 Proceedings
Published on 13. December 2000
Book
Paperback/Softback
XII, 360 pages
978-3-540-41455-1 (ISBN)
Description
These are the pre-proceedings of CHES 2000, the second workshop on Cryp- graphicHardware andEmbedded Systems. The rst workshop, CHES'99, which was held at WPI in August 1999, was received quite enthusiastically by people in academia and industry who are interested in hardware and software imp- mentations of cryptography. We believe there has been a long-standing need for a workshop series combining theory and practice for integrating strong data - curity into modern communications and e-commerce applications. We are very glad that we had the opportunity to serve this purpose and to create the CHES workshop series. As is evident by the papers in these proceedings, there have been many excellentcontributions.Selectingthepapersforthisyear'sCHESwasnotaneasy task, and we regret that we had to reject several good papers due to the limited availability of time. There were 51 submitted contributions to CHES 2000, of which 25 were selected for presentation. This corresponds to a paper acceptance rate of 49% for this year, which is a decrease from the 64% acceptance rate for CHES'99.Allpaperswerereviewed.Inadditiontothecontributedpresentations, we have invited two speakers.
As last year, the focus of the workshop is on all aspects of cryptographic hardware and embedded system design. Of special interest were contributions that describe new methods for e cient hardware implementations and hi- speed software for embedded systems, e.g., smart cards, microprocessors, DSPs, etc. In addition, there were again several very interesting and innovative - pers dealingwith cryptanalysis in practice, rangingfrom side-channel attacks to FPGA-based attack hardware.
As last year, the focus of the workshop is on all aspects of cryptographic hardware and embedded system design. Of special interest were contributions that describe new methods for e cient hardware implementations and hi- speed software for embedded systems, e.g., smart cards, microprocessors, DSPs, etc. In addition, there were again several very interesting and innovative - pers dealingwith cryptanalysis in practice, rangingfrom side-channel attacks to FPGA-based attack hardware.
More details
Series
Edition
2000 ed.
Language
English
Place of publication
Berlin
Germany
Publishing group
Springer Berlin
Target group
Professional and scholarly
Research
Illustrations
XII, 360 p.
Dimensions
Height: 235 mm
Width: 155 mm
Thickness: 21 mm
Weight
563 gr
ISBN-13
978-3-540-41455-1 (9783540414551)
DOI
10.1007/3-540-44499-8
Schweitzer Classification
Other editions
Additional editions
Cetin K. Koc | Christof Paar
Cryptographic Hardware and Embedded Systems - CHES 2000
Second International Workshop Worcester, MA, USA, August 17-18, 2000 Proceedings
E-Book
07/2003
Springer
€53.49
Available for download
Persons
Content
Invited Talk.- Software Implementation of Elliptic Curve Cryptography over Binary Fields.- Implementation of Elliptic Curve Cryptosystems.- Implementation of Elliptic Curve Cryptographic Coprocessor over GF(2m) on an FPGA.- A High-Performance Reconfigurable Elliptic Curve Processor for GF(2m).- Fast Implementation of Elliptic Curve Defined over GF(pm) on CalmRISC with MAC2424 Coprocessor.- Power and Timing Analysis Attacks.- Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies.- Smartly Analyzing the Simplicity and the Power of Simple Power Analysis on Smartcards.- Power Analysis Attacks and Algorithmic Approaches to their Countermeasures for Koblitz Curve Cryptosystems.- A Timing Attack against RSA with the Chinese Remainder Theorem.- Hardware Implementation of Block Ciphers.- A Comparative Study of Performance of AES Final Candidates Using FPGAs.- A Dynamic FPGA Implementation of the Serpent Block Cipher.- A 12 Gbps DES Encryptor/Decryptor Core in an FPGA.- A 155 Mbps Triple-DES Network Encryptor.- Hardware Architectures.- An Energy Efficient Reconfigurable Public-Key Cryptography Processor Architecture.- High-Speed RSA Hardware Based on Barret's Modular Reduction Method.- Data Integrity in Hardware for Modular Arithmetic.- A Design for Modular Exponentiation Coprocessor in Mobile Telecommunication Terminals.- Invited Talk.- How to Explain Side-Channel Leakage to Your Kids.- Power Analysis Attacks.- On Boolean and Arithmetic Masking against Differential Power Analysis.- Using Second-Order Power Analysis to Attack DPA Resistant Software.- Differential Power Analysis in the Presence of Hardware Countermeasures.- Arithmetic Architectures.- Montgomery Multiplier and Squarer in GF(2m).- A Scalable and Unified Multiplier Architecture for FiniteFields GF(p) and GF(2m).- Montgomery Exponentiation with no Final Subtractions: Improved Results.- Physical Security and Cryptanalysis.- Physical Security Devices for Computer Subsystems: A Survey of Attacks and Defenses.- Software-Hardware Trade-Offs: Application to A5/1 Cryptanalysis.- New Schemes and Algorithms.- MiniPASS: Authentication and Digital Signatures in a Constrained Environment.- Efficient Generation of Prime Numbers.