Behavioral Synthesis
Digital System Design Using the Synopsys Behavioral Compiler
Published on 1. July 1996
Book
Paperback/Softback
256 pages
978-0-13-569252-3 (ISBN)
Description
56925-1 Behavioral synthesis is now a reality. After nearly twenty years of academic and industrial research and development, designers are reaping the rewards of this technology, which brings increased productivity, improved design quality, and faster time to market. This book gives a designer's-eye view of this exciting new EDA technology. The first six chapters provide a detailed description of what goes on under the hood of an industrial-strength behavioral synthesis product, the Synopsys Behavioral Compiler, with copious notes and tips on how to use this knowledge to get the most out of this powerful new tool. * Introduction to the behavioral design flow * Behavioral synthesis representations and processes * Writing HDL descriptions for behavioral synthesis * Managing I/O timing * Behavioral Compiler commands and options * Interpreting error messages The next five chapters provide detailed case studies, representing a variety of design problems: * IIR and FIR filters * Video compression and translation from C to HDLs * Data encryption * Packet routing The examples are given in both VHDL and Verilog.
Machine-readable versions, along with complete synthesis reports, are provided on the accompanying diskette (requires Syopsys Behavioral Compiler to synthesize).
Machine-readable versions, along with complete synthesis reports, are provided on the accompanying diskette (requires Syopsys Behavioral Compiler to synthesize).
More details
Language
English
Place of publication
Upper Saddle River
United States
Publishing group
Pearson Education (US)
Target group
College/higher education
Dimensions
Width: 241 mm
Thickness: 24 mm
Weight
734 gr
ISBN-13
978-0-13-569252-3 (9780135692523)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Content
1. Introduction.
Design Flow. Simulation and Verification. RTL and Behavioral Design. Behavioral Compiler Design Flow.
2. Behavioral Compiler.
Inputs. Behavioral Compilation: Internals.
3. HDL Descriptions.
The Design. Behavioral Processes. Clock and Reset. I/O Operations. Flow of Control. Memory Inference. synthetic Components. Preserved Functions. Pipelined Components. Random Logic.
4. I/O Modes.
Cycle-Fixed Mode. Superstate-Fixed Mode. Free-Floating Mode. Control Unit Registers.
5. Explicit Directives and Constraints.
Labeling. Scheduling Constraints. Options. Test Benches; Simulation.
6. Reports.
Timing Report. Reservation Tables. State Machine Reports. Error Messages.
7. FIR Filter.
Initial Design. Synthesis. Simulation. Decreasing Cost.
8. IIR Filter: Handshaking I/O Protocal.
Initial Design. Simulation. Synthesis. Speeding Up the Clock.
9. The Inverse Discrete Cosine Transform: C to HDL.
Initial C Code. Translation into HDL. Simulation.
10. The Data Encryption Standard: Random Logic.
General Description. HDL Description. Synthesis. Use of Design Ware.
11. Packet Router.
A. Construction Design Ware.
B. Sythesizable Subsets.
Design Flow. Simulation and Verification. RTL and Behavioral Design. Behavioral Compiler Design Flow.
2. Behavioral Compiler.
Inputs. Behavioral Compilation: Internals.
3. HDL Descriptions.
The Design. Behavioral Processes. Clock and Reset. I/O Operations. Flow of Control. Memory Inference. synthetic Components. Preserved Functions. Pipelined Components. Random Logic.
4. I/O Modes.
Cycle-Fixed Mode. Superstate-Fixed Mode. Free-Floating Mode. Control Unit Registers.
5. Explicit Directives and Constraints.
Labeling. Scheduling Constraints. Options. Test Benches; Simulation.
6. Reports.
Timing Report. Reservation Tables. State Machine Reports. Error Messages.
7. FIR Filter.
Initial Design. Synthesis. Simulation. Decreasing Cost.
8. IIR Filter: Handshaking I/O Protocal.
Initial Design. Simulation. Synthesis. Speeding Up the Clock.
9. The Inverse Discrete Cosine Transform: C to HDL.
Initial C Code. Translation into HDL. Simulation.
10. The Data Encryption Standard: Random Logic.
General Description. HDL Description. Synthesis. Use of Design Ware.
11. Packet Router.
A. Construction Design Ware.
B. Sythesizable Subsets.