Hardware Accelerator Systems for Artificial Intelligence and Machine Learning: Volume 122
Published on 7. April 2021
Book
Hardback
416 pages
978-0-12-823123-4 (ISBN)
Description
Hardware Accelerator Systems for Artificial Intelligence and Machine Learning, Volume 122 delves into arti?cial Intelligence and the growth it has seen with the advent of Deep Neural Networks (DNNs) and Machine Learning. Updates in this release include chapters on Hardware accelerator systems for artificial intelligence and machine learning, Introduction to Hardware Accelerator Systems for Artificial Intelligence and Machine Learning, Deep Learning with GPUs, Edge Computing Optimization of Deep Learning Models for Specialized Tensor Processing Architectures, Architecture of NPU for DNN, Hardware Architecture for Convolutional Neural Network for Image Processing, FPGA based Neural Network Accelerators, and much more.
More details
Series
Language
English
Place of publication
San Diego
United States
Publishing group
Elsevier Science Publishing Co Inc
Target group
Professional and scholarly
Reference Book for Final year Undergraduate student for Project on Embedded system, Master's and PhD Scholars
Dimensions
Height: 229 mm
Width: 152 mm
Weight
810 gr
ISBN-13
978-0-12-823123-4 (9780128231234)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Other editions
Additional editions
E-Book
03/2021
Academic Press
€130.00
Available for download
Persons
Shiho Kim is a professor in the school of integrated technology at Yonsei University, Seoul, Korea. His previous assignment includes, System on chip design engineer, at LG Semicon Ltd. (currently SK Hynix), Korea, Seoul [1995-1996], Director of RAVERS (Research center for Advanced Hybrid Electric Vehicle Energy Recovery System, a government-supported IT research center. Associate Director of the ICT consilience program, which is a Korea National program for cultivating talented engineers in the field of information and communication Technology, Korea [2011-2012], Director of Seamless Transportation Lab, at Yonsei university, Korea [since 2011-]. His main research interest includes Development of software and hardware technologies for intelligent vehicles, Blockchain technology for intelligent transportation systems, and reinforcement learning for autonomous vehicles. He is the member of the editorial board and reviewer for various Journals and International conferences. So far he has organized 2 International Conference as Technical Chair/General Chair. He is a member of IEIE (Institute of Electronics and Information Engineers of Korea), KSAE (Korean Society of Automotive Engineers), vice president of KINGC (Korean Institute of Next Generation Computing), and a senior member of IEEE. He is the co-author for over 100 papers and holding more than 50 patents in the area of information and communication technology. Ganesh Chandra Deka is currently Deputy Director (Training) at Directorate General of Training, Ministry of Skill Development and Entrepreneurship, Government of India, New Delhi-110001, India. His research interests include e-Governance, Big Data Analytics, NoSQL Databases and Vocational Education and Training.
He has 2 books on Cloud Computing published by LAP Lambert, Germany. He is the Co-author for 4 text books on Fundamentals of Computer Science (3 books published by Moni Manik Prakashan, Guwahati, Assam, India and 1 IGI Global, USA). As of now he has edited 14 books (6 IGI Global, USA, 5 CRC Press, USA, 2 Elsevier & 1 Springer) on Big data, NoSQL and Cloud Computing and authored 10 Book Chapters.
He has published around 47 research papers in various IEEE conferences. He has organized 08 IEEE International Conferences as Technical Chair in India. He is the Member of the editorial board and reviewer for various Journals and International conferences. Member of IEEE, the Institution of Electronics and Telecommunication Engineers, India and Associate Member, the Institution of Engineers, India
He has 2 books on Cloud Computing published by LAP Lambert, Germany. He is the Co-author for 4 text books on Fundamentals of Computer Science (3 books published by Moni Manik Prakashan, Guwahati, Assam, India and 1 IGI Global, USA). As of now he has edited 14 books (6 IGI Global, USA, 5 CRC Press, USA, 2 Elsevier & 1 Springer) on Big data, NoSQL and Cloud Computing and authored 10 Book Chapters.
He has published around 47 research papers in various IEEE conferences. He has organized 08 IEEE International Conferences as Technical Chair in India. He is the Member of the editorial board and reviewer for various Journals and International conferences. Member of IEEE, the Institution of Electronics and Telecommunication Engineers, India and Associate Member, the Institution of Engineers, India
Content
1. Hardware accelerator systems for artificial intelligence and machine learning
Shiho Kim
2. Introduction to Hardware Accelerator Systems for Artificial Intelligence and Machine Learning
Neha Gupta
3. Deep Learning with GPUs
Won Woo Ro
4. Edge Computing Optimization of Deep Learning Models for Specialized Tensor Processing Architectures-Yuri Gordienko
Yuri Gordienko
5. Architecture of NPU for DNN
Kyuho Lee
6. Hardware Architecture for Convolutional Neural Network for Image Processing
Vardhana M
7. FPGA based Neural Network Accelerators
Joo-Young Kim
8. Energy-Efficient Deep Learning Inference on Edge Devices
Massimo Poncino
9. Hardware accelerator systems for Embedded systems
William Jinho Song
10. Generic Quantum Hardware Accelerators for Conventional systems
Parth Bir
11. Music recommender system using Restricted Boltzmann Machine with Implicit Feedback
Malaya Dutta Borah
12. Embedded system for Automated Monitoring in Agriculture and Healthcare
Prashanta Kumar Das
Shiho Kim
2. Introduction to Hardware Accelerator Systems for Artificial Intelligence and Machine Learning
Neha Gupta
3. Deep Learning with GPUs
Won Woo Ro
4. Edge Computing Optimization of Deep Learning Models for Specialized Tensor Processing Architectures-Yuri Gordienko
Yuri Gordienko
5. Architecture of NPU for DNN
Kyuho Lee
6. Hardware Architecture for Convolutional Neural Network for Image Processing
Vardhana M
7. FPGA based Neural Network Accelerators
Joo-Young Kim
8. Energy-Efficient Deep Learning Inference on Edge Devices
Massimo Poncino
9. Hardware accelerator systems for Embedded systems
William Jinho Song
10. Generic Quantum Hardware Accelerators for Conventional systems
Parth Bir
11. Music recommender system using Restricted Boltzmann Machine with Implicit Feedback
Malaya Dutta Borah
12. Embedded system for Automated Monitoring in Agriculture and Healthcare
Prashanta Kumar Das