
Computer Architecture Techniques for Power-Efficiency
Morgan & Claypool Publishers
Published on 30. June 2008
Book
Paperback/Softback
207 pages
978-1-59829-208-4 (ISBN)
Description
In the last few years, power dissipation has become an important design constraint, on par with performance, in the design of new computer systems. Whereas in the past, the primary job of the computer architect was to translate improvements in operating frequency and transistor count into performance, now power efficiency must be taken into account at every step of the design process.
While for some time, architects have been successful in delivering 40% to 50% annual improvement in processor performance, costs that were previously brushed aside eventually caught up. The most critical of these costs is the inexorable increase in power dissipation and power density in processors. Power dissipation issues have catalyzed new topic areas in computer architecture, resulting in a substantial body of work on more power-efficient architectures. Power dissipation coupled with diminishing performance gains, was also the main cause for the switch from single-core to multi-core architectures and a slowdown in frequency increase.
This book aims to document some of the most important architectural techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in processors and memory hierarchies. A significant number of techniques have been proposed for a wide range of situations and this book synthesizes those techniques by focusing on their common characteristics.
While for some time, architects have been successful in delivering 40% to 50% annual improvement in processor performance, costs that were previously brushed aside eventually caught up. The most critical of these costs is the inexorable increase in power dissipation and power density in processors. Power dissipation issues have catalyzed new topic areas in computer architecture, resulting in a substantial body of work on more power-efficient architectures. Power dissipation coupled with diminishing performance gains, was also the main cause for the switch from single-core to multi-core architectures and a slowdown in frequency increase.
This book aims to document some of the most important architectural techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in processors and memory hierarchies. A significant number of techniques have been proposed for a wide range of situations and this book synthesizes those techniques by focusing on their common characteristics.
More details
Series
Language
English
Place of publication
San Rafael
United States
Target group
Professional and scholarly
Dimensions
Height: 235 mm
Width: 187 mm
ISBN-13
978-1-59829-208-4 (9781598292084)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Content
- Introduction
- Modeling, Simulation, and Measurement
- Using Voltage and Frequency Adjustments to Manage Dynamic Power
- Optimizing Capacitance and Switching Activity to Reduce Dynamic Power
- Managing Static (Leakage) Power
- Conclusions
- Modeling, Simulation, and Measurement
- Using Voltage and Frequency Adjustments to Manage Dynamic Power
- Optimizing Capacitance and Switching Activity to Reduce Dynamic Power
- Managing Static (Leakage) Power
- Conclusions