
MIPS RISC Architecture
Prentice Hall (Publisher)
2nd Edition
Published on 1. February 1992
Book
Paperback/Softback
544 pages
978-0-13-590472-5 (ISBN)
Description
A complete reference manual to the MIPS RISC architecture.* describes the user Instruction Set Architecture (ISA), as implemented by the R2000, R3000, R4000, and R6000 (collectively known as the R-Series) processors, together with an extension to this ISA. * describes the general characteristics and capabilities of each RISC processor, along with a description of the programming model, memory management unit (MMU), and the registers associated with each processor. * includes an overview of the underlying concepts that distinguish RISC architecture from Complex Instruction Set Computer (CISC) architecture.
More details
Edition
2nd edition
Language
English
Place of publication
Upper Saddle River
United States
Publishing group
Pearson Education (US)
Target group
College/higher education
Dimensions
Height: 178 mm
Width: 234 mm
Thickness: 22 mm
Weight
839 gr
ISBN-13
978-0-13-590472-5 (9780135904725)
Schweitzer Classification
Content
1. RISC Architecture: An Overview.
2. MIPS Processor Architecture Overview.
3. CPU Instruction Set Summary.
4. Memory Management System.
5. Caches.
6. Exception Processing.
7. FPU Overview.
8. FPU Instruction Set Summary and Instruction Pipeline.
9. Floating Point Exceptions.
Appendixes.
Index.
2. MIPS Processor Architecture Overview.
3. CPU Instruction Set Summary.
4. Memory Management System.
5. Caches.
6. Exception Processing.
7. FPU Overview.
8. FPU Instruction Set Summary and Instruction Pipeline.
9. Floating Point Exceptions.
Appendixes.
Index.