
System Designs into Silicon:
Institute of Physics Publishing
1st Edition
Published on 1. January 1993
Book
Paperback/Softback
192 pages
978-0-7503-0114-5 (ISBN)
Description
Explaining principles and methodology, System Designs into Silicon is an indispensable tool for managers and designers tasked with the evaluation and design of large electronic systems that deal with the movement into integrated circuits. Self-contained and accessible, the book begins at a basic level, gradually building knowledge from chapter to chapter. This enables designers at any level of experience to become familiar with the problems encountered and possible solutions involved. The book also provides a comprehensive glossary of terms to explain much of the jargon associated with the field.
More details
Language
English
Place of publication
London
United Kingdom
Publishing group
Taylor & Francis Ltd
Target group
Professional and scholarly
Electronic systems companies and researchers, electrical and electronic engineers in industry and academia, computer scientists and engineers, and advanced students.
Dimensions
Height: 235 mm
Width: 156 mm
Weight
476 gr
ISBN-13
978-0-7503-0114-5 (9780750301145)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Persons
Content
PART 1
INTRODUCTION
The intention of this book
The silicon explosion
The unexpected problems of VLSI
Programmable silicon
Commercial pressures
The areas of impact
System development-background and current trends
Computer-aided design and engineering
Design for testability
Programmable design options
Hardware programmable
Programmable techniques
Implications of various techniques
The design options
Design productivity
Mixed analogue and digital designs
TECHNOLOGY AND TECHNIQUES
Impact of process developments
Comparison of technologies
ASIC techniques
Standard libraries
Gates
Programmable design options
Programmable techniques
Implications of various techniques
Programmable logic devices
INTERFACE WITH SILICON VENDOR
Choosing a vendor
Design options
Selecting a vendor
Interface to the vendor
PACKAGES
Single chip packaging
Multi-chip packaging
Choosing a package
Chip size
Number of pins
Power dissipation
Package mounting technique
PART 2
DESIGNER'S PROFILE AND DESIGN PRODUCTIVITY
Manpower utilization
Profile of a future designer
Design productivity
DESIGN SUPPORT
Assessing the options
Total ASIC support
Total design support
ANALYSIS OF PROJECT RISKS
Product specification
Motives for the project and project review
Project timescales
Technology
Personnel
Design resource
DESIGN REVIEWS
Aspects of design reviews
Design stages
TRAINING
Training personnel
Computer operating system
CAD tools
Methodology
PART 3
CAD
Requirements of CAD
CAD tools
Software packages
Future
SIMULATION
Simulation modes
Simulator types
Fault simulation
VHDL
HIERARCHICAL PARTITIONING INTO ABSTRACTION LEVELS
System level definitions
Other definitions
SYNTHESIS
Options
Implications of using synthesis
Evolution
Future trends
Synthesizer operation
Performance
Silicon compiler
DESIGN FOR TESTABILITY
Testability design rules
Ad hoc approach to DFT
Structured approach to DFT
DESIGN METHODOLOGY
History
Vertically integrated design methodology
System modeling
Software and hardware partitioning
Behavior coding
Design exploration
Optimization
Top-down
Bottom-up
Comparison
CAD tools
Complexity
Software analogy
PHYSICAL DESIGN-LAYOUT
The options
Floorplanning
Layout modes
Cells
Hierarchy
Placement
Routing
Layout optimization
MIXED ANALOGUE AND DIGITAL DESIGNS
Technologies
Circuit types
CAD tools
Design methodology
Design flow
Analogue design considerations
Test
Interface to silicon vendor
Cost performance
Terminology
PART 4
Appendix
Glossary
Figures
Tables
INTRODUCTION
The intention of this book
The silicon explosion
The unexpected problems of VLSI
Programmable silicon
Commercial pressures
The areas of impact
System development-background and current trends
Computer-aided design and engineering
Design for testability
Programmable design options
Hardware programmable
Programmable techniques
Implications of various techniques
The design options
Design productivity
Mixed analogue and digital designs
TECHNOLOGY AND TECHNIQUES
Impact of process developments
Comparison of technologies
ASIC techniques
Standard libraries
Gates
Programmable design options
Programmable techniques
Implications of various techniques
Programmable logic devices
INTERFACE WITH SILICON VENDOR
Choosing a vendor
Design options
Selecting a vendor
Interface to the vendor
PACKAGES
Single chip packaging
Multi-chip packaging
Choosing a package
Chip size
Number of pins
Power dissipation
Package mounting technique
PART 2
DESIGNER'S PROFILE AND DESIGN PRODUCTIVITY
Manpower utilization
Profile of a future designer
Design productivity
DESIGN SUPPORT
Assessing the options
Total ASIC support
Total design support
ANALYSIS OF PROJECT RISKS
Product specification
Motives for the project and project review
Project timescales
Technology
Personnel
Design resource
DESIGN REVIEWS
Aspects of design reviews
Design stages
TRAINING
Training personnel
Computer operating system
CAD tools
Methodology
PART 3
CAD
Requirements of CAD
CAD tools
Software packages
Future
SIMULATION
Simulation modes
Simulator types
Fault simulation
VHDL
HIERARCHICAL PARTITIONING INTO ABSTRACTION LEVELS
System level definitions
Other definitions
SYNTHESIS
Options
Implications of using synthesis
Evolution
Future trends
Synthesizer operation
Performance
Silicon compiler
DESIGN FOR TESTABILITY
Testability design rules
Ad hoc approach to DFT
Structured approach to DFT
DESIGN METHODOLOGY
History
Vertically integrated design methodology
System modeling
Software and hardware partitioning
Behavior coding
Design exploration
Optimization
Top-down
Bottom-up
Comparison
CAD tools
Complexity
Software analogy
PHYSICAL DESIGN-LAYOUT
The options
Floorplanning
Layout modes
Cells
Hierarchy
Placement
Routing
Layout optimization
MIXED ANALOGUE AND DIGITAL DESIGNS
Technologies
Circuit types
CAD tools
Design methodology
Design flow
Analogue design considerations
Test
Interface to silicon vendor
Cost performance
Terminology
PART 4
Appendix
Glossary
Figures
Tables