Cover: Improving Performance and Reducing Power with Hardware Acceleration - Static Timing Analysis Based Transformations of Combinational Logic in a High Level ASIC Synthesis Flow - VDM Verlag

Improving Performance and Reducing Power with Hardware Acceleration - Static Timing Analysis Based Transformations of Combinational Logic in a High Level ASIC Synthesis Flow

VDM Verlag
Published on 30. December 2008
Book
Paperback/Softback
96 pages
978-3-639-10690-9 (ISBN)
€50.35incl. 7% vat
Shipment within 5-7 days

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