BSIM-Bulk MOSFET Model for IC Design - Digital, Analog, RF and High-Voltage
Published on 3. May 2023
Book
Paperback/Softback
270 pages
978-0-323-85677-5 (ISBN)
Description
BSIM-Bulk MOSFET Model for IC Design - Digital, Analog, RF and High-Voltage provides in-depth knowledge of the internal operation of the model. The authors not only discuss the fundamental core of the model, but also provide details of the recent developments and new real-device effect models. In addition, the book covers the parameter extraction procedures, addressing geometrical scaling, temperatures, and more. There is also a dedicated chapter on extensive quality testing procedures and experimental results. This book discusses every aspect of the model in detail, and hence will be of significant use for the industry and academia.
Those working in the semiconductor industry often run into a variety of problems like model non-convergence or non-physical simulation results. This is largely due to a limited understanding of the internal operations of the model as literature and technical manuals are insufficient. This also creates huge difficulty in developing their own IP models. Similarly, circuit designers and researcher across the globe need to know new features available to them so that the circuits can be more efficiently designed.
Those working in the semiconductor industry often run into a variety of problems like model non-convergence or non-physical simulation results. This is largely due to a limited understanding of the internal operations of the model as literature and technical manuals are insufficient. This also creates huge difficulty in developing their own IP models. Similarly, circuit designers and researcher across the globe need to know new features available to them so that the circuits can be more efficiently designed.
More details
Series
Language
English
Place of publication
United States
Publishing group
Elsevier Science Publishing Co Inc
Target group
Professional and scholarly
Product notice
Paperback (trade)
Illustrations
Approx. 200 illustrations (200 in full color); Illustrations
Dimensions
Height: 229 mm
Width: 152 mm
Thickness: 14 mm
Weight
369 gr
ISBN-13
978-0-323-85677-5 (9780323856775)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Other editions
Additional editions
Chenming Hu | Harshit Agarwal | Chetan Gupta
BSIM-Bulk MOSFET Model for IC Design - Digital, Analog, RF and High-Voltage
E-Book
04/2023
Woodhead Publishing
€195.00
Available for download
Persons
Chenming Hu is TSMC Distinguished Chair Professor Emeritus at the University of California Berkeley, United States. He was the Chief Technology Officer of TSMC. He received the US Presidential Medal of Technology and Innovation from Pres. Barack Obama for developing the first 3D thin-body transistor FinFET, MOSFET reliability models and leading the development of BSIM industry standard transistor model that is used in designing most of the integrated circuits in the world. He is a member of the US Academy of Engineering, the Chinese Academy of Science, and Academia Sinica. He received the highest honor of IEEE, the IEEE Medal of Honor, and its Andrew Grove Award, Solid Circuits Award, and the Nishizawa Medal. He also received the Taiwan Presidential Science Prize and UC Berkeley's highest honor for teaching - the Berkeley Distinguished Teaching Award.
Harshit Agarwal received the PhD degree from Indian Institute of Technology Kanpur, India in 2017. He is currently working as center manager and post-doc fellow at Berkeley Device Modeling Centre, BSIM group, University of California Berkeley, Berkeley, USA. He has been involved in the development of multi-gate and bulk MOSFET models. He is also involved in the modeling and characterization of advanced steep sub-threshold slope devices like negative capacitance FETs, tunnel FET etc. He has authored several papers in the field of semiconductor device modeling, simulation and characterization. He is a Co-Developer of BSIM-BULK (formerly BSIM6) industry standard models for BULK-MOSFET. He has published 8 journal papers and 10 conference papers all on the development of the BSIM-BULK model. His current research interests include semiconductor device physics, modeling, and characterization. Yogesh Singh Chauhan is a Chair Professor in the Department of Electrical Engineering at the Indian Institute of Technology Kanpur, India. He is the developer of several industry standard models: ASM-HEMT, BSIM-BULK (formerly BSIM6), BSIM-CMG, BSIM-IMG, BSIM4 and BSIM-SOI models. His research group is involved in developing compact models for GaN transistors, FinFET, nanosheet/gate-all-around FETs, FDSOI transistors, negative capacitance FETs and 2D FETs. His research interests are RF characterization, modeling, and simulation of semiconductor devices.
Harshit Agarwal received the PhD degree from Indian Institute of Technology Kanpur, India in 2017. He is currently working as center manager and post-doc fellow at Berkeley Device Modeling Centre, BSIM group, University of California Berkeley, Berkeley, USA. He has been involved in the development of multi-gate and bulk MOSFET models. He is also involved in the modeling and characterization of advanced steep sub-threshold slope devices like negative capacitance FETs, tunnel FET etc. He has authored several papers in the field of semiconductor device modeling, simulation and characterization. He is a Co-Developer of BSIM-BULK (formerly BSIM6) industry standard models for BULK-MOSFET. He has published 8 journal papers and 10 conference papers all on the development of the BSIM-BULK model. His current research interests include semiconductor device physics, modeling, and characterization. Yogesh Singh Chauhan is a Chair Professor in the Department of Electrical Engineering at the Indian Institute of Technology Kanpur, India. He is the developer of several industry standard models: ASM-HEMT, BSIM-BULK (formerly BSIM6), BSIM-CMG, BSIM-IMG, BSIM4 and BSIM-SOI models. His research group is involved in developing compact models for GaN transistors, FinFET, nanosheet/gate-all-around FETs, FDSOI transistors, negative capacitance FETs and 2D FETs. His research interests are RF characterization, modeling, and simulation of semiconductor devices.
Author
TSMC Distinguished Chair Professor Emeritus, University of California Berkeley, USA
Center Manager and Postdoctoral Researcher, Berkeley Device Modeling Center, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, USA
Principal Engineer, Micron Technologies, India
Chair Professor, Department of Electrical Engineering, Indian Institute of Technology Kanpur, India
Content
1. Background
2. BSIM-BULK Core Model
3. Real Device Effects
4. Leakage current and thermal effects
5. BSIM-BULK Charge and Capacitance Model
6. Noise and RF Modeling
7. Junction Diode and Layout Dependent Parasitic Model
8. Compact Modeling of High Voltage Devices
9. Parameter Extraction
10. BSIM-BULK Model Quality Testing
2. BSIM-BULK Core Model
3. Real Device Effects
4. Leakage current and thermal effects
5. BSIM-BULK Charge and Capacitance Model
6. Noise and RF Modeling
7. Junction Diode and Layout Dependent Parasitic Model
8. Compact Modeling of High Voltage Devices
9. Parameter Extraction
10. BSIM-BULK Model Quality Testing