Micromechanical studies of interface properties in on-chip interconnect structures

Adhesion testing methods for very small wiring levels in microelectronic devices, the so-called Back-End-of-Line (BEoL), are critical for manufacturing and reliability of modern microelectronic structures. Despite that, measurement techniques for the evaluation of interface properties are scarce. To investigate interfaces at the relevant length scales of interconnect structures was almost impossible with existing techniques until now.
Therefore, nanoindentation-based approaches to test product-like interconnect structures in the size of a few micrometers were developed in this work. The novelty of the method is that interfaces beneath a single via, produced in a standard manufacturing process (copper dual damascene process), can be precisely investigated mechanically at the relevant dimensions. The data generated by these novel methods form the basis for FEM simulations that can help to overcome reliability issues by the improved design of interconnect structures.