Computer Architecture
A Quantitative Approach
3rd Edition
Published on 29. May 2002
Book
Paperback/Softback
1128 pages
978-1-55860-724-8 (ISBN)
Description
This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today. In this edition, the authors bring their trademark method of quantitative analysis not only to high performance desktop machine design, but also to the design of embedded and server systems. They have illustrated their principles with designs from all three of these domains, including examples from consumer electronics, multimedia and web technologies, and high performance computing.The book retains its highly rated features: Fallacies and Pitfalls, which share the hard-won lessons of real designers; Historical Perspectives, which provide a deeper look at computer design history; Putting it all Together, which present a design example that illustrates the principles of the chapter; Worked Examples, which challenge the reader to apply the concepts, theories and methods in smaller scale problems; and Cross-Cutting Issues, which show how the ideas covered in one chapter interact with those presented in others. In addition, a new feature, Another View, presents brief design examples in one of the three domains other than the one chosen for Putting It All Together.The authors present a new organization of the material as well, reducing the overlap with their other text, Computer Organization and Design: A Hardware/Software Approach 2/e, and offering more in-depth treatment of advanced topics in multithreading, instruction level parallelism, VLIW architectures, memory hierarchies, storage devices and network technologies. Also new to this edition, is the adoption of the MIPS 64 as the instruction set architecture. Two new appendixes will be printed in the book: one contains a complete review of the basic concepts of pipelining, the other provides solutions a selection of the exercises. Both will be invaluable to the student or professional learning on her own or in the classroom. Hennessy and Patterson continue to focus on fundamental techniques for designing real machines and for maximizing their cost/performance.
More details
Series
Edition
3rd edition
Language
English
Place of publication
San Francisco
United States
Publishing group
Elsevier Science & Technology
Target group
College/higher education
First year graduate students in Computer Architecture. Anyone involved in designing computers or designing with computers, including architects, computer system engineers, and designers of compilers and operating systems.
Dimensions
Height: 235 mm
Width: 187 mm
Weight
1860 gr
ISBN-13
978-1-55860-724-8 (9781558607248)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Other editions
New editions
John L. Hennessy | David A. Patterson | Christos Kozyrakis
Computer Architecture
A Quantitative Approach
Book
11/2025
7th Edition
Morgan Kaufmann
€104.50
Available immediately
Book
11/2006
4th Edition
Morgan Kaufmann
€54.46
Article exhausted; check for reprint
Persons
ACM named John L. Hennessy a recipient of the 2017 ACM A.M. Turing Award for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry. John L. Hennessy is a Professor of Electrical Engineering and Computer Science at Stanford University, where he has been a member of the faculty since 1977 and was, from 2000 to 2016, its tenth President. Prof. Hennessy is a Fellow of the IEEE and ACM; a member of the National Academy of Engineering, the National Academy of Science, and the American Philosophical Society; and a Fellow of the American Academy of Arts and Sciences. Among his many awards are the 2001 Eckert-Mauchly Award for his contributions to RISC technology, the 2001 Seymour Cray Computer Engineering Award, and the 2000 John von Neumann Award, which he shared with David Patterson. He has also received seven honorary doctorates. ACM named David A. Patterson a recipient of the 2017 ACM A.M. Turing Award for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry. David A. Patterson is the Pardee Chair of Computer Science, Emeritus at the University of California Berkeley. His teaching has been honored by the Distinguished Teaching Award from the University of California, the Karlstrom Award from ACM, and the Mulligan Education Medal and Undergraduate Teaching Award from IEEE. Patterson received the IEEE Technical Achievement Award and the ACM Eckert-Mauchly Award for contributions to RISC, and he shared the IEEE Johnson Information Storage Award for contributions to RAID. He also shared the IEEE John von Neumann Medal and the C & C Prize with John Hennessy. Like his co-author, Patterson is a Fellow of the American Academy of Arts and Sciences, the Computer History Museum, ACM, and IEEE, and he was elected to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. He served on the Information Technology Advisory Committee to the U.S. President, as chair of the CS division in the Berkeley EECS department, as chair of the Computing Research Association, and as President of ACM. This record led to Distinguished Service Awards from ACM, CRA, and SIGARCH.
Content
Foreword
Preface
Acknowledgments
Chapter 1 - Fundamentals of Computer Design
Chapter 2 - Instruction Set Principles and Examples
Chapter 3 - Instruction-Level Parallelism and Its Dynamic Exploitation
Chapter 4 - Exploiting Instruction-Level Parallelism with Software Approaches
Chapter 5 - Memory Hierarchy Design
Chapter 6 - Multiprocessors and Thread-Level Parallelism
Chapter 7 - Storage Systems
Chapter 8 - Interconnection Networks and Clusters
Appendix A - Pipelining: Basic and Intermediate Concepts
Appendix B - Solutions to Selected Exercises Online Appendices
Appendix C - A Survey of RISC Architectures for Desktop, Server, and Embedded Computers
Appendix D - An Alternative to RISC: The Intel 80x86
Appendix E - Another Alternative to RISC: The VAX Architecture
Appendix F - The IBM 360/370 Architecture for Mainframe Computers
Appendix G - Vector Processors Revised by Krste Asanovic
Appendix H - Computer Arithmetic by David Goldberg
Appendix I - Implementing Coherence Protocols
References
Index
Preface
Acknowledgments
Chapter 1 - Fundamentals of Computer Design
Chapter 2 - Instruction Set Principles and Examples
Chapter 3 - Instruction-Level Parallelism and Its Dynamic Exploitation
Chapter 4 - Exploiting Instruction-Level Parallelism with Software Approaches
Chapter 5 - Memory Hierarchy Design
Chapter 6 - Multiprocessors and Thread-Level Parallelism
Chapter 7 - Storage Systems
Chapter 8 - Interconnection Networks and Clusters
Appendix A - Pipelining: Basic and Intermediate Concepts
Appendix B - Solutions to Selected Exercises Online Appendices
Appendix C - A Survey of RISC Architectures for Desktop, Server, and Embedded Computers
Appendix D - An Alternative to RISC: The Intel 80x86
Appendix E - Another Alternative to RISC: The VAX Architecture
Appendix F - The IBM 360/370 Architecture for Mainframe Computers
Appendix G - Vector Processors Revised by Krste Asanovic
Appendix H - Computer Arithmetic by David Goldberg
Appendix I - Implementing Coherence Protocols
References
Index