Microprocessor Architectures
RISC, CISC and DSP
2nd Edition
Published on 31. March 1995
Book
Paperback/Softback
400 pages
978-0-7506-2303-2 (ISBN)
Description
An updated edition reflecting the changes in the industry. Based on several years of involvement with users who have gone through the decision-making process and who have frequently asked many questions, this book covers in-depth RISC, CISC and DSP microprocessor architectures.
More details
Edition
2nd Revised edition
Language
English
Place of publication
Oxford
United Kingdom
Publishing group
Elsevier Science & Technology
Target group
College/higher education
Professional and scholarly
Edition type
Revised edition
Illustrations
200 line drawings, index
Dimensions
Height: 234 mm
Width: 156 mm
Weight
628 gr
ISBN-13
978-0-7506-2303-2 (9780750623032)
Copyright in bibliographic data is held by Nielsen Book Services Limited or its licensors: all rights reserved.
Schweitzer Classification
Other editions
Additional editions
E-Book
06/2014
2nd Edition
Elsevier
€54.95
Available for download
Content
Complex instruction set computers; 32 bit CISC processors; the RISC challenge; RISC wars; digital signal processors; memory, memory management and caches; real time software, interrupts and exceptions; multiprocessing; application examples; semiconductor technology; the changing design cycle; the next generations; selecting a microprocessor architecture; "lies, damn lies and benchmarks"; alternative microprocessor architectures.