Microprocessor Architectures and Systems
RISC, CISC and DSP Processors
Published on 14. January 1991
Book
Paperback/Softback
300 pages
978-0-7506-0032-3 (ISBN)
Description
Intended for both engineers and managers who are given the task of selecting an architecture or design approach, this book examines the developments of Motorola's CISC, RISC and DSP processors. It describes the typical system configurations and engineering trade-offs that are made. The text provides a primer and history of the three basic microprocessor architectures and describes the ways in which the architectures react with the system and covers memory designs, memory management and cache memories. It examines interrupt and exception handling, the effect on real-time applications, basic multiprocessing ideas, shows how certain characteristics can be exploited, looks at semiconductor technology, the changing design cycle and its implications for the design process and commercial success and future processor generations describing the criteria that should be examined when selecting a processor.
More details
Language
English
Place of publication
Oxford
United Kingdom
Publishing group
Elsevier Science & Technology
Target group
Professional and scholarly
Illustrations
index
Dimensions
Height: 234 mm
Width: 156 mm
Weight
64 gr
ISBN-13
978-0-7506-0032-3 (9780750600323)
Copyright in bibliographic data is held by Nielsen Book Services Limited or its licensors: all rights reserved.
Schweitzer Classification
Other editions
Additional editions
E-Book
05/2014
Elsevier
€54.95
Available for download
Content
Part 1 Complex instruction set computers: enter the MC68000; complex instructions, Microcode and Nanocode; the MC68000 hardware; M68000 asynchronousbus; M6800 synchronousbus; the user/supervisor concept; the MC68010 virtual memory processor; MC68010 supervisor resource; the MC68008. Part 2 32-bit CISC processors: enter HCMOS technology; the MC68020 32-bit performance standard; coprocessor interface; MC68881 and MC68882 floating point coprocessors; the MC68851 paged memory management unit (PMMU); the MC68030, the first commercial 50 MHz. Part 3 The rise challenge: the 80/20 rule; the initial RISC research; the Berkeley model; the Stanford model; the catalysts; the M88000 family; the MC88100 programming model; the MC88100 instruction set; MC88100 external functions; M88200 cache MMU; the MBUS protocol; M88000 master/checker fault tolerance. Part 4 Digital signal processing: the DSP56000 family; move commands. Part 5 Memory, memory management and caches: shadow RAM; DRAM v SRAM; optimizing the DRAM interface; memory management; multitasking and user/supervisor conflicts. Part 6 Real time software interrupts and exceptions: interrupting an MC88100; MC88100 interrupt service routines; interrupting the DSP56000; triadic instruction sets; register windowing; the M68300 family. Part 7 Multiprocessing: SISD - single instruction, single data; SIMD - single instruction, multiple data; MIMD - multiple instruction, multiple data; MISD - multiple instruction, single data; constructing a MIMD architecture; processor bandwidths. Part 8 Application ideas: MC68020 and MC68030 design techniques for high-reliability applications; transparent update techniques for digital filters using the DSP56000; motor and servo control. Part 9 Semiconductor technology: semiconductor technology; silicon technology; CMOS and bipolar technology. Part 10 The changing design cycle: the changing design cycle; the shortening design cycle; simulation v emulation. Part 11 Generation: enter the MC68040; the instruction execution unit; the bus interface unit; the M68300 family; DSP96000 combining integration and performance; once a new approach to emulation; integration and higher performance. Part 12 Selecting a microprocessor architecture: meeting performance needs; development support; considering all the options. Appendices: benchmarking; binary compatibility standards.