
Models, Methods, and Tools for Complex Chip Design
Selected Contributions from FDL 2012
Jan Haase(Editor)
Springer (Publisher)
Published on 23. August 2016
Book
Paperback/Softback
XV, 221 pages
978-3-319-34823-0 (ISBN)
Description
This book brings together a selection of the best papers from the fifteenth edition of the Forum on specification and Design Languages Conference (FDL), which was held in September 2012 at Vienna University of Technology, Vienna, Austria. FDL is a well-established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modeling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology systems.
More details
Series
Edition
Softcover reprint of the original 1st ed. 2014
Language
English
Place of publication
Cham
Switzerland
Publishing group
Springer International Publishing
Target group
Professional and scholarly
Illustrations
37 s/w Abbildungen, 57 farbige Abbildungen
XV, 221 p. 94 illus., 57 illus. in color.
Dimensions
Height: 235 mm
Width: 155 mm
Thickness: 13 mm
Weight
414 gr
ISBN-13
978-3-319-34823-0 (9783319348230)
DOI
10.1007/978-3-319-01418-0
Schweitzer Classification
Other editions
Additional editions

Book
10/2013
Springer
€160.49
Shipment within 10-15 days
Content
Formal Plausibility Checks for Environment.- Efficient Refinement Strategy Exploiting Component Properties in A CEGAR Process.- Formal Specification Level.- Power Estimation Methodology for SystemC.- SystemC Analysis for Nondeterminism Anomalies.- A Design and Verification Methodology for Mixed-Signal Systems Using SystemC-AMS.- Configurable Load Emulation Using FPGA and Power Amplifiers for Automotive Power ICs.- Model Based Design of Distributed Embedded Cyber Physical Systems.- Model-driven Methodology for the Development of Multi-level Executable Environments.- The Concept and Study of Grid Responsiveness.- Polynomial Metamodel-Based Fast Optimization of Nanoscale PLL Components.- Methodology and Example-Driven Interconnect Synthesis for Designing Heterogenous Coarse-Grain Reconfigurable Architectures.