ARCS '09

The constantly growing demand on computing performance was satisfied by the increasing clock frequency of the processors in the past. More complex applications use multiple processor cores, starting form dual-cores and ranging to super computers with thousands of computing nodes. Because of problems with the power supply, the power dissipation, and the required cooling of the processor, raising the frequency is no more possible above several gigahertz. Hence, the only possibility to deal with the requirements on computing perfor-mance is to use multi- or even many-core processors. Fortunately, the progress in silicon technology with decreasing structure sizes resulting in higher chip densities enables processor engineers to integrate a high number of processor cores within a single chip. But integrating multiple cores in one chip raises several new questions like the interconnection network, the cache hierarchy and coherency, the memory model as well as new programming paradigms to take advantage of the parallel execution.
The first Workshop on Many-Cores held in conjunction with the ARCS conference 2009 in Delft makes its contribution to these questions. The programme committee selected six papers out of eleven submissions to be presented at the workshop. The papers cover the interconnect-tion network, the cache hierarchy, and case studies on multi- and many-core programming. As invited keynote speaker, Koen de Bosschere presents the new roadmap of the European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC2).