High-speed VLSI Interconnection
Modelling Analysis and Simulation
Ashok K. Goel(Author)
Wiley (Publisher)
Published on 1. April 1994
Book
Hardback
622 pages
978-0-471-57122-3 (ISBN)
Description
Recent advances in very large scale integrated (VLSI) circuit technology have resulted in complex chips with millions of interconnections packed onto a single chip. This causes many problems, including unwanted capacitances, inductances, cross-talk and propagation delays, all of which have serious effects on processor performance. This text is devoted solely to the modelling, analysis and computer simulation of high-speed VLSI interconnections. Source codes of several computer programs for simulating VLSI interconnections and challenging exercises are included at the end of each chapter.
More details
Series
Language
English
Place of publication
New York
United States
Publishing group
John Wiley and Sons Ltd
Target group
College/higher education
Professional and scholarly
Dimensions
Height: 243 mm
Width: 161 mm
Weight
1106 gr
ISBN-13
978-0-471-57122-3 (9780471571223)
Copyright in bibliographic data is held by Nielsen Book Services Limited or its licensors: all rights reserved.
Schweitzer Classification
Content
Preliminary Concepts and More; Parasitic Capacitances and Inductances; Propagation Delays; Cross-talk Analysis; Electromigration-Induced Failure Analysis; Future Interconnection Technologies.