High-Speed VLSI Interconnections
2nd Edition
Will be published approx. on 5. October 2007
Book
Hardback
432 pages
978-0-471-78046-5 (ISBN)
Description
This Second Edition focuses on emerging topics and advances in the field of VLSI interconnections
In the decade since High-Speed VLSI Interconnections was first published, several major developments have taken place in the field. Now, updated to reflect these advancements, this Second Edition includes new information on copper interconnections, nanotechnology circuit interconnects, electromigration in the copper interconnections, parasitic inductances, and RLC models for comprehensive analysis of interconnection delays and crosstalk.
Each chapter is designed to exist independently or as a part of one coherent unit, and several appropriate exercises are provided at the end of each chapter, challenging the reader to gain further insight into the contents being discussed. Chapter subjects include:
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Preliminary Concepts
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Parasitic Resistances, Capacitances, and Inductances
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Interconnection Delays
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Crosstalk Analysis
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Electromigration-Induced Failure Analysis
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Future Interconnections
High-Speed VLSI Interconnections, Second Edition is an indispensable reference for high-speed VLSI designers, RF circuit designers, and advanced students of electrical engineering.
More details
Product info
gebunden
Series
Edition
2. Auflage
Language
English
Place of publication
United States
Publishing group
John Wiley & Sons Inc
Target group
Professional and scholarly
Product notice
sewn/stitched
Cloth over boards
Dimensions
Height: 236 mm
Width: 165 mm
Thickness: 26 mm
Weight
721 gr
ISBN-13
978-0-471-78046-5 (9780471780465)
Schweitzer Classification
Other editions
Additional editions
Ashok K. Goel
High-Speed VLSI Interconnections
E-Book
06/2008
2nd Edition
Wiley
€168.99
Available for download
Person
AShok k. Goel, PhD, is Associate Professor of Electrical Engineering at Michigan Technological University. He is the author of more than thirty journal publications and numerous conference proceedings. His research interests include nanotechnology circuit design, high-speed VLSI interconnections, device physics and modeling, and semiconductor TCAD.
Content
Preface.
1. Preliminary Concepts and More.
Exercises.
References.
2. Parasitic Resistances, Capacitances and Inductances.
Exercises.
References.
3. Interconnection Delays.
Exercises.
References.
4. Crosstalk Analysis.
Exercises.
References.
5. Electromigration-Induced Failure Analysis.
Exercises.
References.
6. Future Interconnections.
Exercises.
References.
CD-ROM.
Appendix 2.1: Listing of the Program "IPCSGV" for Calculating the Parasitic Capacitances for Single Level Interconnections on GaAs-Based VLSI Using the Green's Function Method.
Appendix 2.2: Listing of the Program "ICIMPGV" for Calculating the Parasitic Capacitances and Inductances for Multilevel Interconnections on GaAs-Based VLSI Using the Network Analogue Method.
Appendix 2.3: Listing of the Program "EPCSGM" for Calculating the Electrode Parasitic Capacitances in a Single-Gate GaAs MESFET.
Appendix 3.1: Listing of the Program "PDSIGV" for Calculating the Propagation Delays in the Single Level Interconnections on GaAs-Based VLSI.
Appendix 3.2: Listing of the Program "IPDMSR" for Calculating the Propagation delays in an Interconnection Driven by Minimum Size Repeaters.
Appendix 3.3: Listing of the Program "IPDOSR" for Calculating the Propagation delays in an Interconnection Driven by Optimum Size Repeaters.
Appendix 3.4: Listing of the Program "IPDCR" for Calculating the Propagation delays in an Interconnection Driven by Cascaded Repeaters.
Appendix 4.1: Listing of the Program "DCMPVI" for Delay and Crosstalk Analysis of Multilevel Parallel VLSI Interconnections.
Appendix 4.2: Listing of the Program "SPBIGV" for Signal Propagation Analysis of Bilevel Crossing Interconnections on GaAs-Based VLSI.
Appendix 5.1: Listing of the Program "EMVIC" for Electromigration-Induced Failure Analysis of VLSI Interconnection Components.
Index.