
VLSI-SOC: From Systems to Chips
IFIP TC 10/WG 10.5, Twelfth International Conference on Very Large Scale Ingegration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany
Springer (Publisher)
Published on 17. May 2006
Book
Hardback
X, 314 pages
978-0-387-33402-8 (ISBN)
Description
This book contains extended and revised versions of the best papers that have been presented during the twelfth edition of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration, a Global System-on-a-Chip Design & CAD Conference. The 12* edition was held at the Lufthansa Training Center in Seeheim-Jugenheim, south of Darmstadt, Germany (December 1-3, 2003). Previous conferences have taken place in Edinburgh (81), Trondheim (83), Tokyo (85), Vancouver (87), Munich (89), Edinburgh (91), Grenoble (93), Tokyo (95), Gramado (97), Lisbon (99)andMontpellier(01). The purpose of this conference, sponsored by IFIP TC 10 Working Group 10.5, is to provide a forum to exchange ideas and show research results in the field of microelectronics design. The current trend toward increasing chip integration brings about exhilarating new challenges both at the physical and system-design levels: this conference aims to address these exciting new issues. The 2003 edition of VLSI-SoC conserved the traditional structure, which has been successful in previous editions. The quality of submissions (142 papers) made the selection process difficult, but finally 57 papers and 14 posters were accepted for presentation in VLSI-SoC 2003. Submissions came from Austria, Bulgaria, Brazil, Canada, Egypt, England, Estonia, Finland, France, Germany, Greece, Hungary, India, Iran, Israel, Italy, Japan, Korea, Malaysia, Mexico, Netherlands, Poland, Portugal, Romania, Spain, Sweden, Taiwan and the United States of America. From 57 papers presented at the conference, 18 were selected to have an extended and revised version included in this book.
More details
Series
Edition
and ed.
Language
English
Place of publication
New York
United States
Target group
Professional and scholarly
Researchers and practitioners of microelectronics design
Product notice
sewn/stitched
Cloth over boards
Illustrations
160 s/w Abbildungen
X, 314 p. 160 illus.
Dimensions
Height: 236 mm
Width: 157 mm
Thickness: 25 mm
Weight
658 gr
ISBN-13
978-0-387-33402-8 (9780387334028)
DOI
10.1007/0-387-33403-3
Schweitzer Classification
Other editions
Additional editions

Manfred Glesner | Ricardo Reis | Leandro Indrusiak
VLSI-SOC: From Systems to Chips
IFIP TC 10/WG 10.5, Twelfth International Conference on Very Large Scale Ingegration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany
Book
11/2010
Springer
€106.99
Shipment within 15-20 days
Persons
Content
Effect of Power Optimizations on Soft Error Rate.- Dynamic Models for Substrate Coupling in Mixed-Mode Systems.- Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCs.- Automated Conversion of SystemC Fixed-Point Data Types.- Exploration of Sequential Depth by Evolutionary Algorithms.- Validation of Asynchronous Circuit Specifications Using IF/CADP.- On-Chip Property Verification Using Assertion Processors.- Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems.- A Switched Opamp Based 10 Bits Integrated ADC for Ultra Low Power Applications.- Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based Wlans.- Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures.- Optimizing SOC Test Resources Using Dual Sequences.- A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits.- Low Power Java Processor for Embedded Applications.- Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes.- Evaluation Methodology for Single Electron Encoded Threshold Logic Gates.- Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath.- Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths.- Stuck-At-Fault Testability of SPP Three-Level Logic Forms.