Computer Architecture: A Minimalist Perspective
Published on 5. November 2012
Book
Paperback/Softback
XV, 220 pages
978-1-4613-4980-8 (ISBN)
Description
This book examines computer architecture, computability theory, and the history of computers from the perspective of minimalist computing - a framework in which the instruction set consists of a single instruction. This approach is different than that taken in any other computer architecture text, and it is a bold step. The audience for this book is researchers, computer hardware engineers, software engineers, and systems engineers who are looking for a fresh, unique perspective on computer architecture. Upper division undergraduate students and early graduate students studying computer architecture, computer organization, or embedded systems will also find this book useful. A typical course title might be "Special Topics in Computer Architecture." The organization ofthe book is as follows. First, the reasons for studying such an "esoteric" subject are given. Then, the history and evolution of instruction sets is studied with an emphasis on how modern computing has features ofone instruction computing. Also, previous computer systems are reviewed to show how their features relate to one instruction computers. Next, the primary forms of one instruction set computing are examined. The theories of computation and of Turing machines are also reviewed to examine the theoretical nature of one instruction computers. Other processor architectures and instruction sets are then mapped into single instructions to illustrate the features of both types of one instruction computers. In doing so, the features of the processor being mapped are highlighted.
Reviews / Votes
` This book gives a fine introduction to basic computer architecture. A few years ago, this book would have interested only graduate computer science and engineering students. These days, some high school students even create Linux clusters, and interest in it may be even more widespread. 'R.P. Sarna, Maine Maritime Academy in Choice, December 2003
More details
Series
Edition
Softcover reprint of the original 1st ed. 2003
Language
English
Place of publication
New York
United States
Target group
Professional and scholarly
Research
Illustrations
XV, 220 p.
Dimensions
Height: 235 mm
Width: 155 mm
Thickness: 14 mm
Weight
371 gr
ISBN-13
978-1-4613-4980-8 (9781461349808)
DOI
10.1007/978-1-4615-0237-1
Schweitzer Classification
Other editions
Additional editions
William F. Gilreath | Phillip A. Laplante
Computer Architecture: A Minimalist Perspective
E-Book
12/2012
Springer
€149.79
Available for download
William F. Gilreath | Phillip A. Laplante
Computer Architecture: A Minimalist Perspective
Book
03/2003
1st Edition
Kluwer Academic Publishers
€160.49
Shipment within 15-20 days
Content
1. One Instruction Set Computing.- 1.1 What is One Instruction Set Computing?.- 1.2 Why Study OISC?.- 1.3 A Look Ahead.- 1.4 Exercises.- 2 Instruction Sets.- 2.1 Elements of an Instruction.- 2.2 Operands.- 2.3 Instruction Formats.- 2.4 Core Set of Instructions.- 2.5 Addressing Modes.- 2.6 Exercises.- 3 Types of Computer Architectures.- 3.1 Overview.- 3.2 A Simple Taxonomy.- 3.3 Accumulator.- 3.4 Register-Memory.- 3.5 Register-Oriented.- 3.6 Exercises.- 4 Evolution of Instruction Sets.- 4.1 Motivation.- 4.2 Evolution of Microprocessors.- 4.3 Timeline.- 4.4 Exercises.- 5 CISC, RISC, OISC.- 5.1 CISC versus RISC.- 5.2 Is OISC a CISC or RISC?.- 5.3 Processor Complexity.- 5.4 Exercises.- 6 OISC Architectures.- 6.1 Single Instruction Types.- 6.2 MOVE.- 6.3 Comparing OISC Models.- 6.4 Variants of SBN and MOVE.- 6.5 OISC Continuum.- 6.6 Exercises.- 7 Historical Review of OISC.- 7.1 Subtract and Branch if Negative (SBN).- 7.2 MOVE-based.- 7.3 Timeline.- 7.4 Exercises.- 8 Instruction Set Completeness.- 8.1 Instruction Set Completeness.- 8.2 A Practical Approach to Determining Completeness.- 8.3 Completeness of Two OISCs.- 8.4 Exercises.- 9 OISC Mappings.- 9.1 Mapping OISC to Conventional Architectures.- 9.2 Synthesizing Instructions.- 9.3 Code Fragments.- 9.4 Implementing OISC using OISC.- 9.5 Exercises.- 10 Parallel Architectures.- 10.1 Von Neumann Bottleneck.- 10.2 Parallel Processing.- 10.3 Flynn's Taxonomy for Parallelism.- 10.4 Exercises.- 11 Applications and Implementations.- 11.1 "OlSC-like" Phenomena.- 11.2 Field Programmable Gate Arrays.- 11.3 Applications.- 11.4 Image Processing.- 11.5 Future Work with OISC.- 11.6 Exercises.- Appendix A: A Generic Microprocessor and OISC.- Appendix B: One Instruction Set Computer Implementation.- B.1 6502 Opcodes Summary.- B.2 6502Opcodes Mapped to MOVE OISC.- B.3 6502 Addressing as MOVE-based OISC.- B.4 6502 Addressing Modes and MOVE-based OISC.- Appendix C: Dilation Code Implementation.- Appendix D: Compiler Output for Dilation.- Appendix E: OISC Equivalent of Dilation.- References.- About the Authors.