
Functionality-Enhanced Devices
An alternative to Moore's Law
Pierre-Emmanuel Gaillardon(Editor)
Institution of Engineering and Technology (Publisher)
Published on 23. January 2019
Book
Hardback
344 pages
978-1-78561-558-0 (ISBN)
Description
This book discusses one possible solution to the key issue in electronics engineering - the approaching limits of CMOS scaling - by taking advantage of the tendency of Schottky contacts to form at channel interfaces in nanoscale devices. Rather than suppressing this phenomenon, a functionality-enhanced device exploits it to increase switching functionality. These devices are Multiple-Independent-Gate-Field-Effect-Transistors, and other related nanoscale devices, whose polarity is electrostatically controllable. The functionality enhancement of these devices increases computational performance (function) per unit area and leads to circuits with better density, performance and energy efficiency.
The book provides thorough and systematic coverage of enhanced-functionality devices and their use in proof-of-concept circuits and architectures. The theory and materials science behind these devices are addressed in detail, and various experimental fabrication techniques are explored. In addition, the potential applications of functionality-enhanced devices are outlined with a specific emphasis on circuit design, design automation and benchmarking.
The book provides thorough and systematic coverage of enhanced-functionality devices and their use in proof-of-concept circuits and architectures. The theory and materials science behind these devices are addressed in detail, and various experimental fabrication techniques are explored. In addition, the potential applications of functionality-enhanced devices are outlined with a specific emphasis on circuit design, design automation and benchmarking.
More details
Series
Language
English
Place of publication
Stevenage
United Kingdom
Target group
College/higher education
Professional and scholarly
Product notice
sewn/stitched
Cloth over boards
Dimensions
Height: 236 mm
Width: 163 mm
Thickness: 23 mm
Weight
635 gr
ISBN-13
978-1-78561-558-0 (9781785615580)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Person
Pierre-Emmanuel Gaillardon is an Assistant Professor in the Electrical and Computer Engineering Department and an adjunct assistant professor in the School of Computing at The University of Utah, Salt Lake City, USA where he leads the Laboratory for NanoIntegrated Systems (LNIS). Professor Gaillardon is recipient of the BSF 2017 Prof. Pazy Memorial Research Award, the 2018 NSF CAREER award in functionality-enhanced transistors and the 2018 IEEE CEDA Pederson Award.
Content
Chapter 1: Introduction to functionality-enhanced devices
Part I: Materials and device research related to functionality-enhanced devices
Chapter 2: Germanium-based polarity-controllable transistors
Chapter 3: Two-dimensional materials for functionality-enhanced devices
Chapter 4: Wse2 polarity-controllable devices
Chapter 5: Carrier type control of MX2 type 2D materials for functionality-enhanced transistors
Chapter 6: Three-independent gate FET's super steep subthreshold slope
Chapter 7: Super sensitive terahertz detectors
Part II: Applications and design techniques of functionality-enhanced devices
Chapter 8: CNT and SiNW modeling for dual-gate ambipolar logic circuit design
Chapter 9: Physical design of polarity controllable transistors
Chapter 10: BCB benchmarking for three-independent-gate field effect transistors
Chapter 11: Exploratory logic synthesis for multiple independent gate FETs
Chapter 12: Ultrafine grain FPGAs with polarity controllable transistors
Chapter 13: Tunnel FET-based security primitive design
Part I: Materials and device research related to functionality-enhanced devices
Chapter 2: Germanium-based polarity-controllable transistors
Chapter 3: Two-dimensional materials for functionality-enhanced devices
Chapter 4: Wse2 polarity-controllable devices
Chapter 5: Carrier type control of MX2 type 2D materials for functionality-enhanced transistors
Chapter 6: Three-independent gate FET's super steep subthreshold slope
Chapter 7: Super sensitive terahertz detectors
Part II: Applications and design techniques of functionality-enhanced devices
Chapter 8: CNT and SiNW modeling for dual-gate ambipolar logic circuit design
Chapter 9: Physical design of polarity controllable transistors
Chapter 10: BCB benchmarking for three-independent-gate field effect transistors
Chapter 11: Exploratory logic synthesis for multiple independent gate FETs
Chapter 12: Ultrafine grain FPGAs with polarity controllable transistors
Chapter 13: Tunnel FET-based security primitive design