
Power-Aware Computer Systems
First International Workshop, PACS 2000 Cambridge, MA, USA, November 12, 2000 Revised Papers
Springer (Publisher)
Published on 11. July 2001
Book
Paperback/Softback
X, 158 pages
978-3-540-42329-4 (ISBN)
Description
The phenomenal increases in computer system performance in recent years have been accompanied by a commensurate increase in power and energy dissipation. The latter has directly resulted in demand for expensive packaging and cooling technology, an increase in product cost, and a decrease in product reliability in all segments of the computing market. Moreover, the higher power/energy dissipation has signi cantly reduced battery life in portable systems. While - stem designers have traditionally relied on circuit-level techniques to reduce - wer/energy, there is a growing need to address power/energy dissipation at all levels of the computer system. We are pleased to welcome you to the proceedings of the Power-Aware C- puter Systems (PACS 2000) workshop. PACS 2000 was the rst workshop in its series and its aim was to bring together experts from academia and industry to address power-/energy-awareness at all levels of computer systems. In these p- ceedings, we bring you several excellent research contributions spanning a wide spectrum of areas in power-aware systems, from application all the way to c- pilers and microarchitecture, and to power/performance estimating models and tools. We have grouped the contributions into the following speci c categories: (1) power-aware microarchitectural/circuit techniques, (2) application/compiler power optimizations, (3) exploiting opportunity for power optimization in - struction scheduling and cache memories, and (4) power/performance models and tools.
More details
Series
Edition
2001 ed.
Language
English
Place of publication
Berlin
Germany
Publishing group
Springer Berlin
Target group
Professional and scholarly
Research
Illustrations
X, 158 p.
Dimensions
Height: 235 mm
Width: 155 mm
Thickness: 10 mm
Weight
265 gr
ISBN-13
978-3-540-42329-4 (9783540423294)
DOI
10.1007/3-540-44572-2
Schweitzer Classification
Other editions
Additional editions

B. Falsafi | T.N. Vijaykumar
Power-Aware Computer Systems
First International Workshop, PACS 2000 Cambridge, MA, USA, November 12, 2000 Revised Papers
E-Book
05/2003
Springer
€53.49
Available for download
Content
Power-Aware Microarchitectural/Circuit Techniques.- System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors.- Ramp Up/Down Functional Unit to Reduce Step Power.- An Adaptive Issue Queue for Reduced Power at High Performance.- Application/Compiler Optimizations.- Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform.- Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering.- Compiler-Directed Dynamic Frequency and Voltage Scheduling.- Exploiting IPC/Memory Slack.- Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power.- Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors.- Power/Performance Models and Tools.- TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator.- Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor.- A Comparison of Two Architectural Power Models.