
On-Chip Networks
Morgan & Claypool Publishers
Published on 30. July 2009
Book
Paperback/Softback
141 pages
978-1-59829-584-9 (ISBN)
Description
With the ability to integrate a large number of cores on a single chip, research into on-chip networks to facilitate communication becomes increasingly important. On-chip networks seek to provide a scalable and high-bandwidth communication substrate for multi-core and many-core architectures. High bandwidth and low latency within the on-chip network must be achieved while fitting within tight area and power budgets. In this lecture, we examine various fundamental aspects of on-chip network design and provide the reader with an overview of the current state-of-the-art research in this field.
More details
Series
Language
English
Place of publication
San Rafael
United States
Target group
Professional and scholarly
Dimensions
Height: 235 mm
Width: 187 mm
ISBN-13
978-1-59829-584-9 (9781598295849)
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Schweitzer Classification
Content
- Introduction
- Interface with System Architecture
- Topology
- Routing
- Flow Control
- Router Microarchitecture
- Conclusions
- Interface with System Architecture
- Topology
- Routing
- Flow Control
- Router Microarchitecture
- Conclusions