
Cache and Interconnect Architectures in Multiprocessors
Springer (Publisher)
Published on 19. September 2011
Book
Paperback/Softback
XIV, 277 pages
978-1-4612-8824-4 (ISBN)
Description
Cache And Interconnect Architectures In Multiprocessors Eilat, Israel May 25-261989 Michel Dubois UniversityofSouthernCalifornia Shreekant S. Thakkar SequentComputerSystems The aim of the workshop was to bring together researchers working on cache coherence protocols for shared-memory multiprocessors with various interconnect architectures. Shared-memory multiprocessors have become viable systems for many applications. Bus based shared-memory systems (Eg. Sequent's Symmetry, Encore's Multimax) are currently limited to 32 processors. The fIrst goal of the workshop was to learn about the performance ofapplications on current cache-based systems. The second goal was to learn about new network architectures and protocols for future scalable systems. These protocols and interconnects would allow shared-memory architectures to scale beyond current imitations. The workshop had 20 speakers who talked about their current research. The discussions were lively and cordial enough to keep the participants away from the wonderful sand and sun for two days. The participants got to know each other well and were able to share their thoughts in an informal manner. The workshop was organized into several sessions. The summary of each session is described below. This book presents revisions of some of the papers presented at the workshop.
More details
Edition
Softcover reprint of the original 1st ed. 1990
Language
English
Place of publication
New York
United States
Target group
Professional and scholarly
Research
Illustrations
XIV, 277 p.
Dimensions
Height: 235 mm
Width: 155 mm
Thickness: 17 mm
Weight
452 gr
ISBN-13
978-1-4612-8824-4 (9781461288244)
DOI
10.1007/978-1-4613-1537-7
Schweitzer Classification
Other editions
Additional editions

Michel Dubois | Shreekant S. Thakkar
Cache and Interconnect Architectures in Multiprocessors
E-Book
12/2012
Springer
€96.29
Available for download

Michel Dubois | Shreekant S. Thakkar
Cache and Interconnect Architectures in Multiprocessors
Book
07/1990
Kluwer Academic Publishers
€106.99
Shipment within 15-20 days
Content
TLB Consistency and Virtual Caches.- The Cost of TLB Consistency.- Virtual-Address Caches in Multiprocessors.- Simulation and Performance Studies - Cache Coherence.- A Critique of Trace-Driven Simulation for Shared-Memory Multiprocessors.- Performance of Symmetry Multiprocessor System.- Analysis of Cache Invalidation Patterns in Shared-Memory Multiprocessors.- Memory-Access Penalties in Write-Invalidate Cache Coherence Protocols.- Performance of Parallel Loops using Alternate Cache Consistency Protocols on a Non-Bus Multiprocessor.- Predicting the Performance of Shared Multiprocessor Caches.- Cache Coherence Protocols.- The Cache Coherence Protocol of the Data Diffusion Machine.- SCI (Scalable Coherent Interface) Cache Coherence.- Interconnect Architectures.- Performance Evaluation of Wide Shared Bus Multiprocessors.- Crossbar-Multi-processor Architecture.- "CHESS" Multiprocessor-A Processor-Memory Grid for Parallel Programming.- Software Cache Coherence Schemes.- Software-directed Cache Management in Multiprocessors.