
Guide to RISC Processors
for Programmers and Engineers
Sivarama P. Dandamudi(Author)
Springer (Publisher)
Published on 30. September 2010
Book
Paperback/Softback
XVI, 388 pages
978-1-4419-1935-9 (ISBN)
Description
Recently, there has been a trend toward processors based on the RISC (Reduced Instruction Set Computer) design. This is an accessible and all-encompassing compendium on RISC processors, introducing five of them: MIPS, SPARC, PowerPC, ARM, and Intel's 64-bit Itanium. Initial chapters explain differences between the CISC and RISC designs, and the core RISC design principles are clearly discussed. Later chapters provide instruction on MIPS assembly language programming, so that readers can readily learn the concepts and principles introduced earlier. Professionals, programmers, and students in computer architecture and programming courses will find the guide an essential resource.
More details
Edition
Softcover reprint of hardcover 1st ed. 2005
Language
English
Place of publication
New York
United States
Target group
Professional and scholarly
Professional/practitioner
Product notice
Paperback (trade)
Unsewn / adhesive bound
Illustrations
80 s/w Abbildungen
XVI, 388 p. 80 illus.
Dimensions
Height: 254 mm
Width: 175 mm
Thickness: 25 mm
Weight
717 gr
ISBN-13
978-1-4419-1935-9 (9781441919359)
DOI
10.1007/b139084
Schweitzer Classification
Other editions
Additional editions

Book
02/2005
Springer
€53.49
Shipment within 5-7 days
Content
Overview.- Processor Design Issues.- RISC Principles.- Architectures.- MIPS Architecture.- SPARC Architecture.- PowerPC Architecture.- Itanium Architecture.- ARM Architecture.- MIPS Assembly Language.- SPIM Simulator and Debugger.- Assembly Language Overview.- Procedures and the Stack.- Addressing Modes.- Arithmetic Instructions.- Conditional Execution.- Logical and Shift Operations.- Recursion.- Floating-Point Operations.