Parallel Architectures and Compilation Techniques
Proceedings of the Ifip Wg10.3 Working Conference, Pact '94, Montreal, Canada, 24-26 August 1994
Published on 1. August 1994
Book
Paperback/Softback
374 pages
978-0-444-81926-0 (ISBN)
Description
Fine and medium grain parallelism continues to hold its own as a vital, vibrant research topic. Within the area, new developments in superscalar and VLIW architectures and their associated compilation techniques, have provided exciting new avenues to extract performances from a slowing technology curve. Comprising 28 full-length papers and a number of short (poster) papers, this publication offers a high quality exploration of the current state-of-the art in the field. It should be of particular interest to those involved in control structures and microprogramming; processor architectures; computer systems implementation; programming techniques; and software engineering.
Fine and medium grain parallelism continues to hold its own as a vital, vibrant research topic. Within the area, new developments in superscalar and VLIW architectures and their associated compilation techniques, have provided exciting new avenues to extract performances from a slowing technology curve. Comprising 28 full-length papers and a number of short (poster) papers, this publication offers a high quality exploration of the current state-of-the art in the field. It should be of particular interest to those involved in control structures and microprogramming; processor architectures; computer systems implementation; programming techniques; and software engineering.
Fine and medium grain parallelism continues to hold its own as a vital, vibrant research topic. Within the area, new developments in superscalar and VLIW architectures and their associated compilation techniques, have provided exciting new avenues to extract performances from a slowing technology curve. Comprising 28 full-length papers and a number of short (poster) papers, this publication offers a high quality exploration of the current state-of-the art in the field. It should be of particular interest to those involved in control structures and microprogramming; processor architectures; computer systems implementation; programming techniques; and software engineering.
More details
Series
Language
English
Place of publication
Oxford
United Kingdom
Publishing group
Elsevier Science & Technology
Target group
Professional and scholarly
ISBN-13
978-0-444-81926-0 (9780444819260)
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Schweitzer Classification
Persons
Content
Part 1 High-performance architectures: EM-C - programming with explicit parallelism and locality for EM-4 multiprocessor, M. Sato et al; a fine-grain threaded abstract machine, J. Vasell; tradeoffs in the design of single chip multiprocessors, D.H. Albonesi and I. Koren. Part 2 Code generation for multithreaded and dataflow architectures: an evaluation of optimized threaded code generation, L. Roh et al; functional I-structure and M-structure implementations of NAS Benchmark FT, S. Sur and A.P.W. Bohm; the plan-do style compilation technique for eager data transfer in thread-based execution, M. Yasugi et al. Part 3 Memory and cache issues: a compiler-assisted scheme for adaptive cache coherence enforcement, T.N. Nguyen et al; the impact of cache coherence protocols on systems using fine-grain data synchronization, D.B. Glasco et al; towards a programming environment for a computer with intelligent memory, A. Asthana et al. Part 4 Distributed memory machines: communication analysis for multicomputer compilers, I. Kim and M. Wolfe; automatic data layout using 0-1 integer programming, R. Bixby et al; processor tagged descriptors - a data structure for compiling for distributed-memory multicomputers, E. Su et al. Part 5 Multi-level parallelism: resource spackling - a framework for integrating register allocation in local and global schedulers, D.A. Berson et al; an approach to combine predicted/speculative execution for programs with unpredictable branches, M. Srinivas et al; a PDG-based tool and its use in analyzing program control dependences, C.I. Newburn et al. Part 6 Compiling for parallel machines: static analysis of barrier synchronization in explicitly parallel programs, T.E. Jeremiassen and S.J. Eggers; exploiting the parallelism exposed by partial evaluation, R. Surati and A.A. Berlin; effects of loop fusion and statement migration on the speedup of vector multiprocessors, M. Al-Mouhamed and L. Bic. Part 7 Logic languages: practical static mode analysis of concurrent logic languages, E. Tick; demand-driven dataflow for concurrent committed-choice code, B. Massey and E. Tick; exploitation of fine-grain parallelism in logic languages on massively parallel architectures, H. Kim and J.-L. Gaudiot. Part 8 Application specific architectures: from SIGNAL to fine-grain parallel implementations, O. Maffeis and P. Le Guernic; microcode generation for flexible parallel target architectures, R. Leupers et al; a fleng compiler for PIE64, H. Nakada et al. Part 9 Functional languages, dataflow models and implementation: compiling higher-order functions for tagged-dataflow, R. Rondogiannis and W.W. Wadge; dataflow-based lenient implementation of a functional language, valid, on conventional multi-processors, S. Kusakabe et al; dataflow and logicflow models for defining a parallel prolog abstract machine, P. Kacsuk; towards a computational model for UFO, J. Sargeant et al. (Part Contents).