
VHDL Coding Styles and Methodologies
Ben Cohen(Author)
Kluwer Academic Publishers
Published on 31. August 1995
Book
Hardback
392 pages
978-0-7923-9598-0 (ISBN)
Shipment within 15-20 days
Description
This text offers an in-depth study of the VHDL language rules, coding styles and methodologies. It distinguishes good from poor coding methodologies using a symbology notation along with a rationale for each guideline. The VHDL concepts, rules and styles are demonstrated using complete compilable and simulatable examples which are also supplied on the accompanying disk. The book offers practical applications of VHDL and techniques that are current in the industry. It explains how to apply the VHDL guidelines using several complete examples. The "learning by example" teaching approach along with an in-depth presentation of the language rules application methodology provides the necessary knowledge to create digital hardware designs and models that are readable, maintainable, predictable, and efficient. It is intended for both college students and design engineers, and provides a practical approach to learning VHDL.
More details
Language
English
Place of publication
United States
Target group
College/higher education
Professional and scholarly
Product notice
sewn/stitched
Cloth over boards
Illustrations
index
Dimensions
Height: 260 mm
Width: 183 mm
Thickness: 27 mm
Weight
932 gr
ISBN-13
978-0-7923-9598-0 (9780792395980)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Other editions
New editions

Ben Cohen
VHDL Coding Styles and Methodologies
Book
03/1999
2nd Edition
Kluwer Academic Publishers
€267.49
Shipment within 15-20 days
Additional editions


Ben Cohen
VHDL Coding Styles and Methodologies
E-Book
12/2012
1st Edition
Springer
€53.49
Available for download
Content
1. VHDL Overview and Concepts. 2. Basic Language Elements. 3. Control Structures. 4. Drivers. 5. VHDL Timing. 6. Elements of Entity/Architecture. 7. Subprograms. 8. Packages. 9. User Defined Attributes, Specifications, and Configurations. 10. Functional Models and Testbenches. 11. UART Project. 12. Vital. 13. Design for Synthesis. Appendices: VHDL'93 and VHDL'87 Syntax Summary; Package Standard; Package Textio; Package STD_Logic_1164; VHDL Preferred Attributes.