Very Large Scale Integration Design Methods: Formal Very Large Scale Integration Specification and Synthesis v. 1
International Workshop Proceedings
Luc J. M. Claesen(Editor)
Elsevier (Publisher)
Published in May 1990
Book
Hardback
430 pages
978-0-444-88372-8 (ISBN)
Description
Functional and behavioral verification of correctness forms the bottleneck in current VLSI design systems. For economical reasons, design of VLSI circuits must be completely validated before manufacturing. Current VLSI validation is mainly done through extensive simulation. The emerging alternative is based on formal design and verification methods that guarantee correctness. This book describes original work in all aspects of formal hardware design methods. Topics covered include high-level specification, hardware description languages, formal hardware verification methods, guided synthesis methods, correctness preserving transformations, use of theorem provers for verification, formal proof of correctness, MOS timing verification methods, design for verifiability, and practical experiences.
Functional and behavioral verification of correctness forms the bottleneck in current VLSI design systems. For economical reasons, design of VLSI circuits must be completely validated before manufacturing. Current VLSI validation is mainly done through extensive simulation. The emerging alternative is based on formal design and verification methods that guarantee correctness. This book describes original work in all aspects of formal hardware design methods. Topics covered include high-level specification, hardware description languages, formal hardware verification methods, guided synthesis methods, correctness preserving transformations, use of theorem provers for verification, formal proof of correctness, MOS timing verification methods, design for verifiability, and practical experiences.
Functional and behavioral verification of correctness forms the bottleneck in current VLSI design systems. For economical reasons, design of VLSI circuits must be completely validated before manufacturing. Current VLSI validation is mainly done through extensive simulation. The emerging alternative is based on formal design and verification methods that guarantee correctness. This book describes original work in all aspects of formal hardware design methods. Topics covered include high-level specification, hardware description languages, formal hardware verification methods, guided synthesis methods, correctness preserving transformations, use of theorem provers for verification, formal proof of correctness, MOS timing verification methods, design for verifiability, and practical experiences.
More details
Language
English
Place of publication
Oxford
United Kingdom
Publishing group
Elsevier Science & Technology
Target group
College/higher education
Professional and scholarly
Dimensions
Height: 230 mm
ISBN-13
978-0-444-88372-8 (9780444883728)
Copyright in bibliographic data is held by Nielsen Book Services Limited or its licensors: all rights reserved.
Schweitzer Classification
Content
Guided Synthesis Methods. Boyer-Moore Assisted Specification and Synthesis. Higher Order Logic Based Specification and Synthesis. Specification Formalisms. Formal Design of Regular VLSI Structures. Appendix: Formal Design Benchmark Example.