Advanced Digital Design with the Verilog (TM) HDL + Xilinx 6.3 Student Edition Package

1. Introduction to Digital Design Methodology.


Design Methodology - An Introduction. IC Technology Options. Overview.



2. Review of Combinational Logic Design.


Combinational Logic and Boolean Algebra. Theorems for Boolean Algebraic Minimization. Representation of Combinational Logic. Simplification of Boolean Expressions. Glitches and Hazards. Building Blocks for Logic Design.



3. Fundamentals of Sequential Logic Design.


Storage Elements. Flip-Flops. Busses and Three-State Devices. Design of Sequential Machines. State Transition Graphs. Design Example: BCD to Excess-3 Code Converter. Serial Line Code Converter for Data Transmission. State Reduction and Equivalent States.



4. Introduction to Logic Design with Verilog.


Structural Models of Combinational Logic. Logic Simulation, Design Verification, and Testbenches. Propagation Delay. Truth Table Models of Combinational and Sequential Logic with Verilog.



5. Logic Design with Behavioral Models of Combinational and Sequential Logic.


Behavioral Modeling. A Brief Look at Data Types for Behavioral Modeling. Boolean Equation-Based Behavioral Models of Combinational Logic. Propagation Delay and Continuous Assignments. Latches and Level-Sensitive Circuits in Verilog. Cyclic Behavioral Models of Flip-Flops and Latches. Cyclic Behavior and Edge Detection. A Comparison of Styles for Behavioral Modeling. Behavioral Models of Multiplexers, Encoders, and Decoders. Dataflow Models of a Linear Feedback Shift Register. Modeling Digital Machines with Repetitive Algorithms. Machines with Multi-Cycle Operations. Design Documentation with Functions and Tasks: Legacy or Lunacy? Algorithmic State Machine Charts for Behavioral Modeling. ASMD Charts. Behavioral Models of Counters, Shift Registers, and Register Files. Switch Debounce, Metastability, and Synchronizers for Asynchronous Signals. Design Example: Keypad Scanner and Encoder.



6. Synthesis of Combinational and Sequential Logic.


Introduction to Synthesis. Synthesis of Combinational Logic. Synthesis of Sequential Logic with Latches. Synthesis of Three-State Devices and Bus Interfaces. Synthesis of Sequential Logic with Flip-Flops. Synthesis of Explicit State Machines. Registered Logic. State Encoding. Synthesis of Implicit State Machines, Registers, and Counters. Resets. Synthesis of Gated Clocks and Clock Enables. Anticipating the Results of Synthesis. Synthesis of Loops. Design Traps to Avoid. Divide and Conquer: Partitioning a Design.



7. Design and Synthesis of Datapath Controllers.


Partitioned Sequential Machines. Design Example: Binary Counter. Design and Synthesis of a RISC Stored Program Machine. Design Example: UART.



8. Programmable Logic and Storage Devices.


Programmable Logic Devices. Storage Devices. Programmable Logic Array (PLA). Programmable Array Logic (PALTM). Programmability of PLDs. Complex PLDs (CPLDs). Altera MAX 7000 CPLD. XILINX XC9500 CPLDs. Field Programmable Gate Arrays. Altera Flex 8000 FPGAs. Altera Flex 10 FPGAs. Altera Apex FPGAs. Altera Chip Programmability. XILINX XC4000 Series FPGA. XILINX Spartan XL FPGAs. XILINX Spartan II FPGAs. XILINX Virtex FPGAs. Embeddable and Programmable IP Cores for a System on a Chip (SOC). Verilog-Based Design Flows For FPGAs. Synthesis with FPGAs.



9. Architectures and Algorithms for Digital Processors.


Algorithms, Nested Loop Programs, and Data Flow Graphs. Design Example: Halftone Pixel Image Converter. Digital Filters and Signal Processors. Building Blocks for Signal Processors. Pipelined Architectures. Circular Buffers. Dual-Port Fifos and Synchronization Across Clock Domains.



10. Architectures for Arithmetic Processors.


Number Representation. Functional Units for Addition and Subtraction. Functional Units for Multiplication. Multiplication of Signed Binary Numbers. Multiplication of Fractions. Functional Units for Division.



11. Post-Synthesis Design Tasks.


Post-Synthesis Design Validation. Post-Synthesis Timing Verification. Elimination of ASIC Timing Violations. False Paths. Dynamically Sensitized Paths. System Tasks for Timing Verification. Fault Simulation and Testing. Fault Simulation. Fault Simulation with Verifault-XL. JTAG Ports and Design for Testability and BIST.



Appendices.


Verilog Primitives. Verilog Keywords. Verilog Nets. Verilog Data Types, Operators, and Precedence. Backus-Naur (BNF) Formal Syntax Notation. Verilog Language Formal Syntax. System Tasks and Functions. Compiler Directives. Rules for User Defined Primitives. Additional Features of Verilog. Verilog 2001. PLI. Websites. Web-based Tutorials.



Index.