VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design
20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers
Published on 24. August 2016
Book
Paperback/Softback
X, 235 pages
978-3-662-52529-6 (ISBN)
Description
This book contains extended and revised versions of the best papers presented at the 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, held in Santa Cruz, CA, USA, in October 2012. The 12 papers included in the book were carefully reviewed and selected from the 33 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the current trend toward increasing chip integration and technology process advancements bringing about stimulating new challenges both at the physical and system-design levels, as well as in the test of these systems.
More details
Series
Edition
Softcover reprint of the original 1st ed. 2013
Language
English
Place of publication
Berlin
Germany
Publishing group
Springer Berlin
Target group
Professional and scholarly
Illustrations
121 farbige Abbildungen
X, 235 p. 121 illus. in color.
Dimensions
Height: 235 mm
Width: 155 mm
Thickness: 14 mm
Weight
382 gr
ISBN-13
978-3-662-52529-6 (9783662525296)
DOI
10.1007/978-3-642-45073-0
Schweitzer Classification
Other editions
Additional editions
Andreas Burg | Ayse Coskun | Matthew Guthaus
VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design
20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers
Book
11/2013
Springer
€53.49
Shipment within 7-9 days
Persons
Content
FPGA-Based High-Speed Authenticated Encryption System.- A Smart Memory Accelerated Computed Tomography Parallel Backprojection.- Trinocular Stereo Vision Using a Multi Level Hierarchical Classification Structure.- Spatially-Varying Image Warping: Evaluations and VLSI Implementations.- An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing.- Configurable Low-Latency Interconnect for Multi-core Clusters.- A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks.- Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnections.- On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors.- SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture.- CMOS Implementation of Threshold Gates with Hysteresis.- Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates.