Energy Efficient Microprocessor Design
Published on 5. November 2012
Book
Paperback/Softback
XII, 357 pages
978-1-4613-5282-2 (ISBN)
Description
This work began in 1995 as an outgrowth of the InfoPad project which showed us that in order to reduce the energy consumption of a portable multimedia terminal that something had to be done about the consumption of the microprocessor subsystem. The design of the InfoPad attempted to reduce the requirements of this general pur pose processor by moving the computation into the network or by the use of highly optimized integrated circuits, but in spite of these efforts it still was a major consumer of energy. The reasons for this became apparent as we determined that the energy required to perform a function in dedicated hardware could be several orders of magnitude lower than that consumed in the InfoPad microprocessor. We therefore set out on a full fledged attack on all aspects of the microprocessor energy consumption [1 J. After considerable analysis it became clear that though better circuit design and a stream lined architecture would assist in our goal of energy reduction, that the biggest gains were to be found by operating at reduced voltages. For the busses and VO this could be accomplished without significant degradation of the processor performance, but this was not a straightforward solution when applied to the core of the processor sub system (CPU and memory).
More details
Edition
Softcover reprint of the original 1st ed. 2002
Language
English
Place of publication
New York
United States
Target group
Professional and scholarly
Research
Illustrations
XII, 357 p.
Dimensions
Height: 235 mm
Width: 155 mm
Thickness: 21 mm
Weight
563 gr
ISBN-13
978-1-4613-5282-2 (9781461352822)
DOI
10.1007/978-1-4615-0875-5
Schweitzer Classification
Other editions
Additional editions
Thomas D. Burd | Robert W. Brodersen
Energy Efficient Microprocessor Design
E-Book
12/2012
Springer
€96.29
Available for download
Thomas D. Burd | Robert W. Brodersen
Energy Efficient Microprocessor Design
Book
10/2001
Springer
€106.99
Shipment within 15-20 days
Content
1 Introduction.- 1.1 The Need for Energy Efficiency.- 1.2 The Performance-Energy Trade-off.- 1.3 Book Organization.- 2 Energy Efficient Design.- 2.1 Processor Usage Model.- 2.2 CMOS Circuit Models.- 2.3 Energy Use Metrics.- 2.4 Energy Efficient Design Observations.- 2.5 Dynamic Voltage Scaling.- 3 Microprocessor System Architecture.- 3.1 System Architecture.- 3.2 Processor Core.- 3.3 Cache System.- 3.4 System Coprocessor.- 3.5 Summary.- 4 Circuit Design Methodology.- 4.1 General Energy-Efficient Circuit Design.- 4.2 Memory Design.- 4.3 Low-Swing Bus Transceivers.- 4.4 Design Constraints Over Voltage.- 4.5 Design Constraints for Varying Voltage.- 5 Energy Driven Design Flow.- 5.1 Overview.- 5.2 High-level Energy Estimation.- 5.3 Clocking Methodology.- 5.4 Power Distribution Methodology.- 5.5 Functional Verification.- 5.6 Timing Verification.- 6 Microprocessor and Memory IC's.- 6.1 Microprocessor IC.- 6.2 Processor Architecture.- 6.3 Memory IC.- 7 DC-DC Voltage Conversion.- 7.1 Introduction to Switching Regulators.- 7.2 PWM Operation.- 7.3 PFM Operation.- 7.4 Other Topologies.- 7.5 Dynamic Voltage Conversion.- 8 DC-DC Converter IC for DVS.- 8.1 System and Algorithm Description.- 8.2 External Component Selection.- 8.3 Frequency Detector.- 8.4 Current Comparators.- 8.5 Power FETs.- 8.6 Efficiency Simulations.- 8.7 Measured Results.- 9 DVS System Design and Results.- 9.1 System Architecture.- 9.2 Interface IC.- 9.3 Prototype Board.- 9.4 Software Infrastructure.- 9.5 Evaluation.- 9.6 Comparisons and other related work.- 10 Software and Operating System Support.- 10.1 Software Energy Reduction.- 10.2 Software Environment.- 10.3 System Architecture.- 10.4 Benchmarking.- 10.5 DVS Operating System.- 10.6 Voltage Scheduling Algorithms.- 10.7 Algorithm Analysis.- 10.8 Commentsand Possible Further Directions.- 11 Conclusions.- 11.1 Energy Efficient Design.- 11.2 Current Industry Directions.- 11.3 Future Directions.