This book constitutes the proceedings of the 33rd International Conference on Architecture of Computing Systems, ARCS 2020, held in Aachen, Germany, in May 2020.*
The 12 full papers in this volume were carefully reviewed and selected from 33 submissions. 6 workshop papers are also included. ARCS has always been a conference attracting leading-edge research outcomes in Computer Architecture and Operating Systems, including a wide spectrum of topics ranging from embedded and real-time systems all the way to large-scale and parallel systems. The selected papers focus on concepts and tools for incorporating self-adaptation and self-organization mechanisms in high-performance computing systems. This includes upcoming approaches for runtime modifications at various abstraction levels, ranging from hardware changes to goal changes and their impact on architectures, technologies, and languages.
*The conference was canceled due to the COVID-19 pandemic.
Series
Edition
Language
Place of publication
Publishing group
Springer International Publishing
Target group
Professional and scholarly
Illustrations
50 s/w Abbildungen, 62 farbige Abbildungen
XII, 257 p. 112 illus., 62 illus. in color.
Dimensions
Height: 235 mm
Width: 155 mm
Thickness: 15 mm
Weight
ISBN-13
978-3-030-52793-8 (9783030527938)
DOI
10.1007/978-3-030-52794-5
Schweitzer Classification
Main Conference.-
Approximate Data Dependence Pro ling based on Abstract Interval and Congruent Domains.- Evaluating Dynamic Task Scheduling with Priorities and Adaptive Aging in a Task-based Runtime System.- An Architecture for Solving the Eigenvalue Problem on Embedded FPGAs.- ECC Memory for Fault Tolerant RISC-V Processors.- 3D Optimisation of Software Application Mappings on Heterogeneous MPSoCs.- Towards a Priority-Based Task Distribution Strategy for an Artificial Hormone System.- He..ro DB: A Concept for Parallel Data Processing on Heterogeneous Hardware.- Investigating Transactional Memory for High Performance Embedded Systems.- X-CEL: A Method to Estimate Near-Memory Acceleration Potential in Tile-based MPSoCs.- Engineering an Optimized Instruction Set Architecture for AMIDAR Processors.- Scaling Logic Locking Schemes to Multi-Module Hardware Designs.- Exploration of Power Domain Partitioning with Concurrent Task Mapping and Scheduling for Application-specific Multi-core SoCs.-
FORMUS
3
IC Workshop.-
Scalable, Decentralized Battery Management System Based on Self-Organizing Nodes.- Security Improvements by Separating the Cryptographic Protocol from the Network Stack onto a Multi-MCU Architecture.- Equally Distributed Bus-Communication Access Rights for Inter MCU Communication using Multimaster SPI.-
Workshop on Computer Architectures in Space (CompSpace).-
On the Evaluation of SEU Effects on AXI Interconnect within AP-SoCs.- Satellite Onboard Data Reduction using a Risc-V core inside an RTG4-based Data Processing Pipeline.-
Workshop on Parallel Systems and Algorithms (PASA).-
Accelerating Real-Time Applications with Predictable Work-Stealing.
