Nonvolatile Memory Technologies with Emphasis on Flash
A Comprehensive Guide to Understanding and Using Flash Memory Devices
1st Edition
Published on 1. February 2008
Book
Hardback
792 pages
978-0-471-77002-2 (ISBN)
Description
Presented here is an all-inclusive treatment of Flash technology, including Flash memory chips, Flash embedded in logic, binary cell Flash, and multilevel cell Flash. The book begins with a tutorial of elementary concepts to orient readers who are less familiar with the subject. Next, it covers all aspects and variations of Flash technology at a mature engineering level: basic device structures, principles of operation, related process technologies, circuit design, overall design tradeoffs, device testing, reliability, and applications.
More details
Series
Language
English
Place of publication
United States
Publishing group
John Wiley & Sons Inc
Target group
Professional and scholarly
Illustrations
Photos: 25 B&W, 0 Color; Drawings: 670 B&W, 0 Color
Dimensions
Height: 262 mm
Width: 187 mm
Thickness: 41 mm
Weight
1497 gr
ISBN-13
978-0-471-77002-2 (9780471770022)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Other editions
Additional editions
Joe Brewer | Manzur Gill
Nonvolatile Memory Technologies with Emphasis on Flash
A Comprehensive Guide to Understanding and Using Flash Memory Devices
E-Book
09/2011
Wiley-IEEE Press
€179.99
Available for download
Joe Brewer | Manzur Gill
Nonvolatile Memory Technologies with Emphasis on Flash
A Comprehensive Guide to Understanding and Using Flash Memory Devices
E-Book
06/2008
Wiley-IEEE Press
€179.99
Available for download
Persons
Joe E. Brewer, MS, spent most of his career with Westinghouse Electric (now Northrop Grumman Corporation), where he retired in 1998. In 2000, he joined the faculty of the Electrical and Computer Engineering Department of the University of Florida. He was an early contributor to the IEEE Standards for MNOS Arrays and Floating Gate Arrays. He is a Fellow of the IEEE, has authored more than 100 papers, and holds seven U.S. patents. Manzur Gill, PhD, is Chief Advancement Officer and Professor of Physics at Forman Christian College, Lahore, in Pakistan. Dr. Gill has more than twenty-five years of experience in high-tech industry and nonvolatile memory development, has authored over thirty technical publications in international journals, and holds over seventy-five patents.
Content
Foreword. Preface.
Contributors.
1 INTRODUCTION TO NONVOLATILE MEMORY (Joe E. Brewer).
1.1 Introduction.
1.2 Elementary Memory Concepts.
1.3 Unique Aspects of Nonvolatile Memory.
1.4 Flash Memory and Flash Cell Variations.
1.5 Semiconductor Device Technology Generations.
2 FLASH MEMORY APPLICATIONS (Gary Forni, Collin Ong, Christine Rice, Ken McKee, and Ronald J. Bauer).
2.1 Introduction.
2.2 Code Storage.
2.3 Data Storage.
2.4 Code+Data Storage.
2.5 Conclusion.
3 MEMORY CIRCUIT TECHNOLOGIES (Giulio G. Marotta, Giovanni Naso, and Giuseppe Savarese).
3.1 Introduction.
3.2 Flash Cell Basic Operation.
3.3 Flash Memory Architecture.
3.4 Redundancy.
3.5 Error Correction Coding (ECC).
3.6 Design for Testability (DFT).
3.7 Flash-Specifi c Circuit Techniques.
4 PHYSICS OF FLASH MEMORIES (J. Van Houdt, R. Degraeve, G. Groeseneken, and H. E. Maes).
4.1 Introduction.
4.2 Basic Operating Principles and Memory Characteristics.
4.3 Physics of Programming and Erase Mechanisms.
4.4 Physics of Degradation and Disturb Mechanisms.
4.5 Conclusion.
5 NOR FLASH STACKED AND SPLIT-GATE MEMORY TECHNOLOGY (Stephen N. Keeney, Manzur Gill, and David Sweetman).
5.1 Introduction.
5.2 ETOX Flash Cell Technology.
5.3 SST SuperFlash EEPROM Cell Technology.
5.4 Reliability Issues and Solutions.
5.5 Applications.
6 NAND FLASH MEMORY TECHNOLOGY (Koji Sakui and Kang-Deog Suh).
6.1 Overview of NAND EEPROM.
6.2 NAND Cell Operation.
6.3 NAND Array Architecture and Operation.
6.4 Program Threshold Control and Program Vt Spread Reduction.
6.5 Process and Scaling Issues.
6.6 Key Circuits and Circuit/Technology Interactions.
6.7 Multilevel NAND.
7 DINOR FLASH MEMORY TECHNOLOGY (Moriyoshi Nakashima and Natsuo Ajika).
7.1 Introduction.
7.2 DINOR Operation and Array Architecture.
7.3 DINOR Technology Features.
7.4 DINOR Circuit for Low-Voltage Operation.
7.5 Background Operation Function.
7.6 P-Channel DINOR Architecture.
8 P-CHANNEL FLASH MEMORY TECHNOLOGY (Frank Ruei-Ling Lin and Charles Ching-Hsiang Hsu).
8.1 Introduction.
8.2 Device Structure.
8.3 Operations of P-Channel Flash.
8.4 Array Architecture of P-Channel Flash.
8.5 Evolution of P-Channel Flash.
8.6 Processing Technology for P-Channel Flash.
9 EMBEDDED FLASH MEMORY (Chang-Kiang (Clinton) Kuo and Ko-Min Chang).
9.1 Introduction.
9.2 Embedded Flash Versus Stand-Alone Flash Memory.
9.3 Embedded Flash Memory Applications.
9.4 Embedded Flash Memory Cells.
9.5 Embedded Flash Memory Design.
10 TUNNEL DIELECTRICS FOR SCALED FLASH MEMORY CELLS (T. P. Ma).
10.1 Introduction.
10.2 SiO2 as Tunnel Dielectric-Historical Perspective.
10.3 Early Work on Silicon Nitride as a Tunnel Dielectric.
10.4 Jet-Vapor Deposition Silicon Nitride Deposition.
10.5 Properties of Gate-Quality JVD Silicon Nitride Films.
10.6 Deposited Silicon Nitride as Tunnel Dielectric.
10.7 N-Channel Floating-Gate Device with Deposited Silicon Nitride Tunnel Dielectric.
10.8 P-Channel Floating-Gate Device with Deposited Silicon Nitride Tunnel Dielectric.
10.9 Reliability Concerns Associated with Hot-Hole Injection.
10.10 Tunnel Dielectric for SONOS Cell.
10.11 Prospects for High-K Dielectrics.
10.12 Tunnel Barrier Engineering with Multiple Barriers.
10.13 Summary.
11 FLASH MEMORY RELIABILITY (Jian Justin Chen, Neal R. Mielke, and Chenming Calvin Hu).
11.1 Introduction.
11.2 Cycling-Induced Degradations in Flash Memories.
11.3 Flash Memory Data Retention.
11.4 Flash Memory Disturbs.
11.5 Stress-Induced Tunnel Oxide Leakage Current.
11.6 Special Reliability Issues for Poly-to-Poly Erase and Source-Side Injection Program.
11.7 Process Impacts on Flash Memory Reliability.
11.8 High-Voltage Periphery Transistor Reliability.
11.9 Design and System Impacts on Flash Memory Reliability.
11.10 Flash Memory Reliability Screening and Qualifi cation.
11.11 For Further Study.
12 MULTILEVEL CELL DIGITAL MEMORIES (Albert Fazio and Mark Bauer).
12.1 Introduction.
12.2 Pursuit of Low-Cost Memory.
12.3 Multibit Storage Breakthrough.
12.4 View of MLC Today.
12.5 Low-Cost Design Implementation.
12.6 Low-Cost Process Manufacturing.
12.7 Standard Product Feature Set.
12.8 Further Reading: Multilevel Flash Memory and Technology Scaling.
12.9 Conclusion.
13 ALTERNATIVE MEMORY TECHNOLOGIES (Gary F. Derbenwick and Joe E. Brewer).
13.1 Introduction.
13.2 Limitations of Flash Memory.
13.3 NROM Memories.
13.4 Ferroelectric Memories.
13.5 Magnetic Memories.
13.6 Single-Electron and Few-Electron Memories.
13.7 Resistive and Hybrid CMOS/Nanodevice Memories.
13.8 NOVORAM/FRAM Cell and Architecture.
13.9 Phase Change Memories.
Index.
About the Editors.
Contributors.
1 INTRODUCTION TO NONVOLATILE MEMORY (Joe E. Brewer).
1.1 Introduction.
1.2 Elementary Memory Concepts.
1.3 Unique Aspects of Nonvolatile Memory.
1.4 Flash Memory and Flash Cell Variations.
1.5 Semiconductor Device Technology Generations.
2 FLASH MEMORY APPLICATIONS (Gary Forni, Collin Ong, Christine Rice, Ken McKee, and Ronald J. Bauer).
2.1 Introduction.
2.2 Code Storage.
2.3 Data Storage.
2.4 Code+Data Storage.
2.5 Conclusion.
3 MEMORY CIRCUIT TECHNOLOGIES (Giulio G. Marotta, Giovanni Naso, and Giuseppe Savarese).
3.1 Introduction.
3.2 Flash Cell Basic Operation.
3.3 Flash Memory Architecture.
3.4 Redundancy.
3.5 Error Correction Coding (ECC).
3.6 Design for Testability (DFT).
3.7 Flash-Specifi c Circuit Techniques.
4 PHYSICS OF FLASH MEMORIES (J. Van Houdt, R. Degraeve, G. Groeseneken, and H. E. Maes).
4.1 Introduction.
4.2 Basic Operating Principles and Memory Characteristics.
4.3 Physics of Programming and Erase Mechanisms.
4.4 Physics of Degradation and Disturb Mechanisms.
4.5 Conclusion.
5 NOR FLASH STACKED AND SPLIT-GATE MEMORY TECHNOLOGY (Stephen N. Keeney, Manzur Gill, and David Sweetman).
5.1 Introduction.
5.2 ETOX Flash Cell Technology.
5.3 SST SuperFlash EEPROM Cell Technology.
5.4 Reliability Issues and Solutions.
5.5 Applications.
6 NAND FLASH MEMORY TECHNOLOGY (Koji Sakui and Kang-Deog Suh).
6.1 Overview of NAND EEPROM.
6.2 NAND Cell Operation.
6.3 NAND Array Architecture and Operation.
6.4 Program Threshold Control and Program Vt Spread Reduction.
6.5 Process and Scaling Issues.
6.6 Key Circuits and Circuit/Technology Interactions.
6.7 Multilevel NAND.
7 DINOR FLASH MEMORY TECHNOLOGY (Moriyoshi Nakashima and Natsuo Ajika).
7.1 Introduction.
7.2 DINOR Operation and Array Architecture.
7.3 DINOR Technology Features.
7.4 DINOR Circuit for Low-Voltage Operation.
7.5 Background Operation Function.
7.6 P-Channel DINOR Architecture.
8 P-CHANNEL FLASH MEMORY TECHNOLOGY (Frank Ruei-Ling Lin and Charles Ching-Hsiang Hsu).
8.1 Introduction.
8.2 Device Structure.
8.3 Operations of P-Channel Flash.
8.4 Array Architecture of P-Channel Flash.
8.5 Evolution of P-Channel Flash.
8.6 Processing Technology for P-Channel Flash.
9 EMBEDDED FLASH MEMORY (Chang-Kiang (Clinton) Kuo and Ko-Min Chang).
9.1 Introduction.
9.2 Embedded Flash Versus Stand-Alone Flash Memory.
9.3 Embedded Flash Memory Applications.
9.4 Embedded Flash Memory Cells.
9.5 Embedded Flash Memory Design.
10 TUNNEL DIELECTRICS FOR SCALED FLASH MEMORY CELLS (T. P. Ma).
10.1 Introduction.
10.2 SiO2 as Tunnel Dielectric-Historical Perspective.
10.3 Early Work on Silicon Nitride as a Tunnel Dielectric.
10.4 Jet-Vapor Deposition Silicon Nitride Deposition.
10.5 Properties of Gate-Quality JVD Silicon Nitride Films.
10.6 Deposited Silicon Nitride as Tunnel Dielectric.
10.7 N-Channel Floating-Gate Device with Deposited Silicon Nitride Tunnel Dielectric.
10.8 P-Channel Floating-Gate Device with Deposited Silicon Nitride Tunnel Dielectric.
10.9 Reliability Concerns Associated with Hot-Hole Injection.
10.10 Tunnel Dielectric for SONOS Cell.
10.11 Prospects for High-K Dielectrics.
10.12 Tunnel Barrier Engineering with Multiple Barriers.
10.13 Summary.
11 FLASH MEMORY RELIABILITY (Jian Justin Chen, Neal R. Mielke, and Chenming Calvin Hu).
11.1 Introduction.
11.2 Cycling-Induced Degradations in Flash Memories.
11.3 Flash Memory Data Retention.
11.4 Flash Memory Disturbs.
11.5 Stress-Induced Tunnel Oxide Leakage Current.
11.6 Special Reliability Issues for Poly-to-Poly Erase and Source-Side Injection Program.
11.7 Process Impacts on Flash Memory Reliability.
11.8 High-Voltage Periphery Transistor Reliability.
11.9 Design and System Impacts on Flash Memory Reliability.
11.10 Flash Memory Reliability Screening and Qualifi cation.
11.11 For Further Study.
12 MULTILEVEL CELL DIGITAL MEMORIES (Albert Fazio and Mark Bauer).
12.1 Introduction.
12.2 Pursuit of Low-Cost Memory.
12.3 Multibit Storage Breakthrough.
12.4 View of MLC Today.
12.5 Low-Cost Design Implementation.
12.6 Low-Cost Process Manufacturing.
12.7 Standard Product Feature Set.
12.8 Further Reading: Multilevel Flash Memory and Technology Scaling.
12.9 Conclusion.
13 ALTERNATIVE MEMORY TECHNOLOGIES (Gary F. Derbenwick and Joe E. Brewer).
13.1 Introduction.
13.2 Limitations of Flash Memory.
13.3 NROM Memories.
13.4 Ferroelectric Memories.
13.5 Magnetic Memories.
13.6 Single-Electron and Few-Electron Memories.
13.7 Resistive and Hybrid CMOS/Nanodevice Memories.
13.8 NOVORAM/FRAM Cell and Architecture.
13.9 Phase Change Memories.
Index.
About the Editors.