Modern electronics depend on nanoscaled technologies that present new challenges in terms of testing and diagnostics. Memories are particularly prone to defects since they exploit the technology limits to get the highest density. This book is an invaluable guide to the testing and diagnostics of the latest generation of SRAM, one of the most widely applied types of memory. Classical methods for testing memory are designed to handle the so-called "static faults," but these test solutions are not sufficient for faults that are emerging in the latest Very Deep Sub-Micron (VDSM) technologies. These new fault models, referred to as "dynamic faults", are not covered by classical test solutions and require the dedicated test sequences presented in this book.
Edition
Language
Place of publication
Target group
Professional and scholarly
Research
Illustrations
Dimensions
Height: 235 mm
Width: 155 mm
Thickness: 11 mm
Weight
ISBN-13
978-1-4899-8314-5 (9781489983145)
DOI
10.1007/978-1-4419-0938-1
Schweitzer Classification
Gennaro Severino Rodrigues got his Ph.D. in Microelectronics from the Universidade Federal do Rio Grande do Sul (UFRGS, Porto Alegre, Brazil), in cooperation with LIRMM (Montpellier, France) and the Ecole Centrale de Lyon (France). His research is focused on Approximate Computing and Fault Tolerance, and he has been working on the development of embedded software for safety-critical applications and fault tolerance techniques. His interests are also in Machine Learning and its relation to approximate computing and fault tolerance.
Fernanda Lima Kastensmidt is a Full Professor at Instituto de Informatica, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brasil. She has bachelor's at Engenharia Elétrica from Universidade Federal do Rio Grande do Sul (1997), master's at Computer Science from Universidade Federal do Rio Grande do Sul (1999) and doctorate at Computer Science from Universidade Federaldo Rio Grande do Sul (2003). Has experience in Computer Science, focusing on Hardware, acting on the following subjects: fault tolerance, radhard systems, FPGAs, fault modeling. She is author of the book: Fault Tolerance Techniques for SRAM-based FPGAs published in 2006 by Springer and co-author of other 3 books. She has developed part of the payload of NanoSat-BR1 satellite that was launched on June 2104. And she is currently working in the payload of NanoSAT-BR2, launched at 2021.
Alberto Bosio received the PhD in Computer Engineering from the Politecnico di Torino, Italy in 2006. He is a Full Professor at the Institute of Nanotechnology - Ecole Centrale de Lyon (France). His research interests include Approximate Computing, In-Memory Computing, Reliability, Test and Diagnosis of Digital circuits and systems. He co-authored 4 books, 4 patents 54 journals, and over 164 conference papers. He served as committee member in prestigious international conferences as DAC and DATE, as well as guest editors for ACM, IEEE and ELSEVIER journals. He is the vice-chair of the Europeen Test Technical Technology Council (eTTTC) and a member of the IEEE.
Basics on SRAM Testing.- Resistive-Open Defects in Core-Cells.- Resistive-Open Defects in Pre-charge Circuits.- Resistive-Open Defects in Address Decoders.- Resistive-Open Defects in Write Drivers.- Resistive-Open Defects in Sense Amplifiers.- Faults Due to Process Variations in SRAMs.- Diagnosis and Design-for-Diagnosis.