Specification and Validation Methods
Egon Borger(Author)
Clarendon Press
Published on 1. August 1995
Book
Hardback
469 pages
978-0-19-853854-7 (ISBN)
Description
The book combines a high-level introduction to the state of the art with the development of new methods for specification and validation of computing systems. The methods are elaborated for challenging and characteristic applications, spanning from semantics of programming languages and their implementation (PROLOG,CLPC(R) and CLAM,C++) to architecture design (VHDL), including also parallel and distributed programs as well as protocols (Kermit for example). The eleven chapters are written in a self-contained way, each by a leading expert. The book is unique for two reasons: it combines a state-of-the-art survey with a systematic presentation of recent advances, based on new ideas and approaches; its themes range from software to hardware design and the proposed methods are applied to specification and validation of complex real-life computing systems. This book is intended for researchers and graduate students in computer science. Systems programmers.
More details
Language
English
Place of publication
Oxford
United Kingdom
Publishing group
Oxford University Press
Target group
College/higher education
Professional and scholarly
Illustrations
line figures, bibliography
ISBN-13
978-0-19-853854-7 (9780198538547)
Copyright in bibliographic data is held by Nielsen Book Services Limited or its licensors: all rights reserved.
Schweitzer Classification
Content
Introduction. 1.: Evolving algebras 1993. Lipari guide. 2.: Annotated bibliography on evolving algebras. 3.: Program verification and Prolog. 4.: CLAM-specifications for provably correct compilation of CLP(R) program. 5.: The semantics of the C++ programming language. 6.: Verification of parameterized programs VHDL-based system-level hardware design. 7.: The Bakery Algorithm: yet another specification and verification. 8.: Kermit: specification and verification. 9.: Group membership protocol: specification and verification. 10.: Specification and verification of VHDL-based system-level hardware design. 11.: Specification and verification of Gate-level VHDL models of synchronous and asynchronous circuits