
Programmable Reed-Solomon Codec
Design and Implementation
LAP Lambert Academic Publishing
Published on 19. September 2013
Book
Paperback/Softback
64 pages
978-3-659-45726-5 (ISBN)
Description
The modern communications systems become faster day by day. Errors almost inevitably occur during the transmission, storage or processing of information, because of noise and interference in communication channels, or imperfections in storage media. Therefore, the detection and correction of errors in information have become very important issue. Reed-Solomon (RS) codes are non-binary, cyclic error correcting codes which are very much effective for the detection and correction of burst errors. RS codes are defined over Galois field. The encoder appends parity symbols to the data using a predetermined algorithm before transmission. Decoder detects and corrects errors. VLSI design creates a flexible and high degree of parallelism for implementing the RS codes. The purpose of this thesis is to design and implement a programmable RS encoder and decoder on an FPGA platform. In this work, a modified architecture for a programmable RS encoder and decoder has been proposed. Employing the proposed scheme, RS codes can be generated and decoded for different generator polynomials. Also an RS (255, 251) encoder and decoder have been implemented on an FPGA platform.
More details
Language
English
Dimensions
Height: 220 mm
Width: 150 mm
Thickness: 5 mm
Weight
113 gr
ISBN-13
978-3-659-45726-5 (9783659457265)
Schweitzer Classification
Persons
Dr. J. Bhaumik is working as an Asoc. Prof. in the Dept. of ECE, HIT. He obtained his PhD degree from IIT Kharagpur. He received his B.Tech & M.Tech from CU. His research areas: VLSI, ECC & Cryptography. Mr. S. Das is working as a SRF at CR Rao AIMSCS. He did his B.Tech & M.Tech in ECE from WBUT. His research areas: Cryptology, Big Data Analytics.