
Domain-Specific Processors
Systems, Architectures, Modeling, and Simulation
CRC Press
1st Edition
Published on 11. November 2003
Book
Hardback
280 pages
978-0-8247-4711-4 (ISBN)
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Description
Ranging from low-level application and architecture optimizations to high-level modeling and exploration concerns, this authoritative reference compiles essential research on various levels of abstraction appearing in embedded systems and software design. It promotes platform-based design for improved system implementation and modeling and enhanced performance and cost analyses. Domain-Specific Processors relies upon notions of concurrency and parallelism to satisfy performance and cost constraints resulting from increasingly complex applications and architectures and addresses concepts in specification, simulation, and verification in embedded systems and software design.
More details
Series
Language
English
Place of publication
Bosa Roca
United States
Publishing group
Taylor & Francis Inc
Target group
Professional and scholarly
Professional
Dimensions
Height: 280 mm
Width: 210 mm
Weight
498 gr
ISBN-13
978-0-8247-4711-4 (9780824747114)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Other editions
Additional editions

Shuvra S. Bhattacharyya | Ed F. Deprettere | Joergen Teich
Domain-Specific Processors
Systems, Architectures, Modeling, and Simulation
E-Book
11/2003
1st Edition
CRC Press
€59.49
Available for download

Shuvra S. Bhattacharyya | Ed F. Deprettere | Joergen Teich
Domain-Specific Processors
Systems, Architectures, Modeling, and Simulation
E-Book
11/2003
CRC Press
€59.49
Available for download
Content
Automatic VHDL Model Generation of Parameterized FIR Filters, E.George Walters III, John Glossner, Michael J. Schulte; An LUT-Based High Level Synthesis Framework for Reconfigurable Architectures Lo c Lagadec, Bernard Pottier, and Oscar Villellas-Guillen; Highly Efficient Scalable Parallel-Pipelined Architectures for Discrete Wavelet Transforms David Guevorkian, Petri Liuha, Aki Launiainen and Ville Lappalainen; Stride Permutation Access in Interleaved Memory Systems, Jarmo Takala and Tuomas Jarvinen; Modelling of Intra-task Parallelism in Task-level Parallel Embedded Systems, Andy D. Pimentel, Frank P. Terpstra, Simon Polstra and Joe E. Coffland; Energy Estimation and Optimization for Piecewise Regular Processor Arrays, Frank Hannig and, Juergen Teich; Automatic Synthesis of Efficient Interfaces for Compiled Regular Architectures, Steven Derrien, Anne-Claire Quillou, Patrice Quinton, Tanguy Risset and Charles Wagner; Goal-Driven Reconfiguration of Polymorphous Architectures, Sumit Lohani and Shuvra S. Bhattacharyya; Realizations of the Extended Linearization Model, Alexandru Turjan, Bart Kienhuis, Ed Deprettere; Communication Services for Networks on Chip, Andrei Radulescu and Kees Goossens; Single chip Multiprocessing for Consumer Electronics, Paul Stravers and Jan Hoogerbugge; Future Directions of (Programmable and Reconfigurable) Embedded Processors, Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana.