Formal Methods for Hardware Verification
6th International School on Formal Methods for the Design of Computer, Communication, and Software Systems, SFM 2006, Bertinoro, Italy, May 22-27, 2006, Advances Lectures
Published on 15. May 2006
Book
Paperback/Softback
VIII, 244 pages
978-3-540-34304-2 (ISBN)
Description
This book presents 8 papers accompanying the lectures of leading researchers given at the 6th edition of the International School on Formal Methods for the Design of Computer, Communication and Software Systems (SFM 2006). SFM 2006 was devoted to formal techniques for hardware verification and covers several aspects of the hardware design process, including hardware design languages and simulation, property specification formalisms, automatic test pattern generation, symbolic trajectory evaluation, and more.
More details
Series
Edition
2006 ed.
Language
English
Place of publication
Berlin
Germany
Publishing group
Springer Berlin
Target group
Professional and scholarly
Research
Illustrations
VIII, 244 p.
Dimensions
Height: 23.5 cm
Width: 15.5 cm
Weight
800 gr
ISBN-13
978-3-540-34304-2 (9783540343042)
DOI
10.1007/11757283
Schweitzer Classification
Content
Hardware Design and Simulation for Verification.- Automatic Test Pattern Generation.- An Introduction to Symbolic Trajectory Evaluation.- BDD-Based Hardware Verification.- SAT-Based Verification Methods and Applications in Hardware Verification.- Building Efficient Decision Procedures on Top of SAT Solvers.- Refinement and Theorem Proving.- Floating-Point Verification Using Theorem Proving.