
Logic-timing Simulation And The Degradation Delay Model
Imperial College Press
Will be published approx. on 30. November 2005
Book
Hardback
288 pages
978-1-86094-589-2 (ISBN)
Description
This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the "Degradation Delay Model", developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the application cases and accuracy of logic-timing simulation. These ideas are supported by simulation results extracted from a wide range of practical applications.Sample Chapter(s)
More details
Language
English
Place of publication
London
United Kingdom
Target group
College/higher education
Professional and scholarly
Product notice
sewn/stitched
Paper over boards
Dimensions
Height: 228 mm
Width: 162 mm
Thickness: 22 mm
Weight
531 gr
ISBN-13
978-1-86094-589-2 (9781860945892)
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Schweitzer Classification
Persons
Author
Univ De Sevilla, Spain
Univ De Sevilla, Spain
Univ De Sevilla, Spain
Content
# Fundamentals of Timing Simulation # Delay Models: Evolution and Trends # Degradation and Inertial Effects # CMOS Inverter Degradation Delay Model # Gate-Level DDM # Logic Level Simulator Design and Implementation # DDM Simulation Results # Accurate Measurement of the Switching Activity