
Innovations in the Memory System
Rajeev Balasubramonian(Author)
Springer (Publisher)
Published on 10. September 2019
Book
Paperback/Softback
XXI, 129 pages
978-3-031-00635-7 (ISBN)
Description
The memory system has the potential to be a hub for future innovation. While conventional memory systems focused primarily on high density, other memory system metrics like energy, security, and reliability are grabbing modern research headlines. With processor performance stagnating, it is also time to consider new programming models that move some application computations into the memory system. This, in turn, will lead to feature-rich memory systems with new interfaces. The past decade has seen a number of memory system innovations that point to this future where the memory system will be much more than dense rows of unintelligent bits. This book takes a tour through recent and prominent research works, touching upon new DRAM chip designs and technologies, near data processing approaches, new memory channel architectures, techniques to tolerate the overheads of refresh and fault tolerance, security attacks and mitigations, and memory scheduling.
More details
Series
Language
English
Place of publication
Cham
Switzerland
Publishing group
Springer International Publishing
Target group
Professional and scholarly
Illustrations
XXI, 129 p.
Dimensions
Height: 235 mm
Width: 191 mm
Thickness: 9 mm
Weight
298 gr
ISBN-13
978-3-031-00635-7 (9783031006357)
DOI
10.1007/978-3-031-01763-6
Schweitzer Classification
Other editions
Additional editions

Rajeev Balasubramonian
Innovations in the Memory System
E-Book
05/2022
Springer
€64.19
Available for download
Person
Rajeev Balasubramonian is a Professor at the School of Computing, University of Utah. He received his B.Tech. in Computer Science and Engineering from the Indian Institute of Technology, Bombay in 1998. He received his M.S. (2000)and Ph.D. (2003) from the University of Rochester. His primary research interests include memory systems, security, and application-specific architectures. Prof. Balasubramonian is a recipient of an NSF CAREER award, faculty research awards from IBM, Google, HPE, an Intel Outstanding Research Award, and various teaching awards at the University of Utah. He has co-authored papers that have been selected as IEEE Micro Top Picks (2007 and 2010) and that have received three best paper awards.
Content
List of Figures.- List of Tables.- Preface.- Acknowledgments.- Introduction.- Memory System Basics for Every Architect.- Commercial Memory Products.- Memory Scheduling.- Data Placement.- Memory Chip Microarchitectures.- Memory Channels.- Memory Reliability.- Memory Refresh.- Near Data Processing.- Memory Security.- Closing Thoughts.- Bibliography.- Author's Biography.