
The Designer's Guide to VHDL
Peter J. Ashenden(Author)
Morgan Kaufmann (Publisher)
2nd Edition
Published on 5. June 2001
Book
Paperback/Softback
768 pages
978-1-55860-674-6 (ISBN)
Description
Since the publication of the first edition of The Designer's Guide to VHDL in 1996, digital electronic systems have increased exponentially in their complexity, product lifetimes have dramatically shrunk, and reliability requirements have shot through the roof. As a result more and more designers have turned to VHDL to help them dramatically improve productivity as well as the quality of their designs. VHDL, the IEEE standard hardware description language for describing digital electronic systems, allows engineers to describe the structure and specify the function of a digital system as well as simulate and test it before manufacturing. In addition, designers use VHDL to synthesize a more detailed structure of the design, freeing them to concentrate on more strategic design decisions and reduce time to market. Adopted by designers around the world, the VHDL family of standards have recently been revised to address a range of issues, including portability across synthesis tools. This best-selling comprehensive tutorial for the language and authoritative reference on its use in hardware design at all levels--from system to gates--has been revised to reflect the new IEEE standard, VHDL-2001. Peter Ashenden, a member of the IEEE VHDL standards committee, presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Reviewers on Amazon.com have consistently rated the first edition with five stars. This second edition updates the first, retaining the authors unique ability to teach this complex subject to a broad audience of students and practicing professionals.
Reviews / Votes
"The second edition of The Designer's Guide to VHDL sets a new standard in VHDL texts. I am certain that you will find it a very valuable addition to your library." --From the foreword by Paul Menchini, Menchini & AssociatesMore details
Series
Edition
2nd edition
Language
English
Place of publication
San Francisco
United States
Publishing group
Elsevier Science & Technology
Target group
Professional and scholarly
Edition type
New edition
Dimensions
Height: 235 mm
Width: 187 mm
Weight
1270 gr
ISBN-13
978-1-55860-674-6 (9781558606746)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Other editions
Additional editions

Peter J. Ashenden
The Designer's Guide to VHDL
E-Book
06/2001
2nd Edition
Morgan Kaufmann
€66.95
Available for download
Previous edition
Author M. Unknown
The Designer's Guide to VHDL
Book
11/1995
Morgan Kaufmann
€63.32
Article exhausted; check for reprint
Person
Peter J. Ashenden received his B.Sc.(Hons) and Ph.D. from the University of Adelaide, Australia. He was previously a senior lecturer in computer science and is now a Visiting Research Fellow at the University of Adelaide. His research interests are computer organization and electronic design automation. Dr. Ashenden is also an independent consultant specializing in electronic design automation (EDA). He is actively involved in IEEE working groups developing VHDL standards, is the author of The Designer's Guide to VHDL and The Student's Guide to VHDL and co-editor of the Morgan Kaufmann series, Systems on Silicon. He is a senior member of the IEEE and a member of the ACM.
Author
Adjunct Associate Professor, School of Computer Science, University of Adelaide, Australia
Content
1 Fundamental Concepts2 Scalar Data Types and Operations3 Sequential Statements4 Composite Data Types and Operations5 Basic Modeling Constructs6 Case Study: A Pipelined Multiplier Accumulator7 Subprograms8 Packages and Use Clauses9 Aliases10 Case Study: A Bit-Vector Arithmetic Package11 Resolved Signals12 Generic Constants13 Components and Configurations14 Generate Statements15 Case Study: The DLX Computer System16 Guards and Blocks17 Access Types and Abstract Data Types18 Files and Input/Output19 Case Study: Queuing Networks20 Attributes and Groups21 Miscellaneous TopicsA SynthesisB The Predefined Package StandardC IEEE Standard PackagesD Related StandardsE VHDL SyntaxF DifferencesG Answers to ExercisesReferencesIndex