The Designer's Guide to VHDL: Volume 3
Volume 3
3rd Edition
Published on 1. July 2008
Book
Hardback
936 pages
978-0-12-088785-9 (ISBN)
Description
VHDL, the IEEE standard hardware description language for describing digital electronic systems, has recently been revised. The Designer's Guide to VHDL has become a standard in the industry for learning the features of VHDL and using it to verify hardware designs. This third edition is the first comprehensive book on the market to address the new features of VHDL-2008.
More details
Series
Edition
3rd edition
Language
English
Place of publication
San Francisco
United States
Publishing group
Elsevier Science & Technology
Target group
College/higher education
Hardware Verification Engineers using VHDL
Product notice
sewn/stitched
Paper over boards
Dimensions
Height: 244 mm
Width: 195 mm
Thickness: 50 mm
Weight
2049 gr
ISBN-13
978-0-12-088785-9 (9780120887859)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Other editions
Additional editions
Peter J. Ashenden
The Designer's Guide to VHDL
E-Book
10/2010
3rd Edition
Morgan Kaufmann
€52.95
Available for download
Person
Peter J. Ashenden received his B.Sc.(Hons) and Ph.D. from the University of Adelaide, Australia. He was previously a senior lecturer in computer science and is now a Visiting Research Fellow at the University of Adelaide. His research interests are computer organization and electronic design automation. Dr. Ashenden is also an independent consultant specializing in electronic design automation (EDA). He is actively involved in IEEE working groups developing VHDL standards, is the author of The Designer's Guide to VHDL and The Student's Guide to VHDL and co-editor of the Morgan Kaufmann series, Systems on Silicon. He is a senior member of the IEEE and a member of the ACM.
Content
1. Fundamental Concepts
2. Scalar Data Types and Operations
3. Sequential Statements
4. Composite Data Types and Operations
5. Basic Modeling Constructs
6. Case Study: A Pipelined Complex Multiplier Accumulator
7. Subprograms
8. Packages and Use Clauses
9. Aliases
10. External Names in Testbenches
11. Properties and Assertion-Based Design
12. Resolved Signals
13. Generics
14. Components and Configurations
15. Generate Statements
16. Access Types and Abstract Data Types
17. Files and Input/Output
18. Case Study: Queuing Networks
19. Attributes and Groups
20. Design for Synthesis
21. Case Study: System Design using the Gumnut Core
22. Miscellaneous Topics
Appendix
A. Standard Packages
B. Related Standards
C. VHDL Syntax
D. Differences Among VHDL Versions
E. Answers to Exercises
2. Scalar Data Types and Operations
3. Sequential Statements
4. Composite Data Types and Operations
5. Basic Modeling Constructs
6. Case Study: A Pipelined Complex Multiplier Accumulator
7. Subprograms
8. Packages and Use Clauses
9. Aliases
10. External Names in Testbenches
11. Properties and Assertion-Based Design
12. Resolved Signals
13. Generics
14. Components and Configurations
15. Generate Statements
16. Access Types and Abstract Data Types
17. Files and Input/Output
18. Case Study: Queuing Networks
19. Attributes and Groups
20. Design for Synthesis
21. Case Study: System Design using the Gumnut Core
22. Miscellaneous Topics
Appendix
A. Standard Packages
B. Related Standards
C. VHDL Syntax
D. Differences Among VHDL Versions
E. Answers to Exercises