Co-verification of Hardware and Software for ARM SoC Design
Published on 4. September 2004
Book
Paperback/Softback
288 pages
978-0-7506-7730-1 (ISBN)
Description
Hardware/software co-verification is how to make sure that embedded system software works correctly with the hardware, and that the hardware has been properly designed to run the software successfully -before large sums are spent on prototypes or manufacturing. This is the first book to apply this verification technique to the rapidly growing field of embedded systems-on-a-chip(SoC). As traditional embedded system design evolves into single-chip design, embedded engineers must be armed with the necessary information to make educated decisions about which tools and methodology to deploy. SoC verification requires a mix of expertise from the disciplines of microprocessor and computer architecture, logic design and simulation, and C and Assembly language embedded software. Until now, the relevant information on how it all fits together has not been available. Andrews, a recognized expert, provides in-depth information about how co-verification really works, how to be successful using it, and pitfalls to avoid. He illustrates these concepts using concrete examples with the ARM core - a technology that has the dominant market share in embedded system product design. The companion CD-ROM contains all source code used in the design examples, a searchable e-book version, and useful design tools.
Reviews / Votes
"Jason Andrews is one of the acknowledged world's experts in hardware/software verification. His unique knowledge, spanning both hardware design and software development, has enabled him to come up with breakthrough design tools and methodologies solving many of today's most pressing verification challenges. This is one of the most important books to come on the scene in the last ten years." Gary Smith, Chief Analyst, Design & Engineering, Gartner DataquestMore details
Language
English
Place of publication
Oxford
United Kingdom
Publishing group
Elsevier Science & Technology
Target group
Professional and scholarly
Embedded systems engineers and programmers, verification engineers, engineering production managers.
Electrical/software engineering students, electronics
technicians working in embedded systems, inhouse training departments of electronics
manufacturers.
Dimensions
Height: 235 mm
Width: 191 mm
Weight
610 gr
ISBN-13
978-0-7506-7730-1 (9780750677301)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Other editions
Additional editions
E-Book
05/2014
Newnes
€62.95
Available for download
Person
Jason Andrews is currently working in the areas of hardware/software co-verification and testbench methodology for SoC design at Verisity. He has implemented multiple commercial co-verification tools as well as many custom co-verification solutions. His experience in the EDA and embedded marketplace includes software development and product management at Verisity, Axis Systems, Simpod, Summit Design, and Simulation Technologies. He has presented technical papers and tutorials at the Embedded Systems Conference, Communication Design Conference and IP/SoC and written numerous articles related to HW/SW co-verification and design verification. He has a B.S. in electrical engineering from The Citadel, Charleston, S.C., and an M.S. in electrical engineering from the University of Minnesota. He currently lives in the Minneapolis area with his wife, Deborah, and their four children.
Content
1. Embedded System Verification2. Hardware and Software Design Process: System initialization software and hardware abstraction layer (HAL), Hardware diagnostic test suite, Real-time operating system (RTOS), RTOS device drivers, Application software, C simulation, Logic simulation, Simulation acceleration, Emulation, Prototype; 3. SoC Verification Topics for the ARM Architecture; 4. Hardware/Software Co-Verification: Host-code execution - implicit access, ISS + BIM, CCM, RTL, Hardware model,Emulation board, FPGA Prototype; 5. Advanced Hardware/Software Co-Verification: Direct access to simulation memories without advancing simulation time, Memory and time optimizations - understanding synchronization, Cross network connections versus using a single workstation, C modeling for some of the hardware, Implicit Access,Post-processing techniques for software debugging, Synchronized software and hardware views for debugging, Post-processing software trace, Save/restore, How to deal with peripherals, How to deal with an RTOS; 6. Hardware Verification Environment and Co-Verification: Testbench, The use of testbench tools, Random test generation based on CPU address map, CPU bus protocol checking, Functional/ Transaction coverage, Memory coverage, Property checking - did a specific scenario ever happen? Use of a design signoff model;7. Methodology for an Example ARM SoC.