This book provides a unified treatment of Flip-Flop design and selection in nanometer CMOS VLSI systems. The design aspects related to the energy-delay tradeoff in Flip-Flops are discussed, including their energy-optimal selection according to the targeted application, and the detailed circuit design in nanometer CMOS VLSI systems. Design strategies are derived in a coherent framework that includes explicitly nanometer effects, including leakage, layout parasitics and process/voltage/temperature variations, as main advances over the existing body of work in the field. The related design tradeoffs are explored in a wide range of applications and the related energy-performance targets. A wide range of existing and recently proposed Flip-Flop topologies are discussed. Theoretical foundations are provided to set the stage for the derivation of design guidelines, and emphasis is given on practical aspects and consequences of the presented results. Analytical models and derivations are introduced when needed to gain an insight into the inter-dependence of design parameters under practical constraints. This book serves as a valuable reference for practicing engineers working in the VLSI design area, and as text book for senior undergraduate, graduate and postgraduate students (already familiar with digital circuits and timing).
Edition
Softcover reprint of the original 1st ed. 2015
Language
Place of publication
Publishing group
Springer International Publishing
Target group
Professional and scholarly
Illustrations
118 s/w Abbildungen, 5 farbige Abbildungen
XV, 260 p. 123 illus., 5 illus. in color.
Dimensions
Height: 235 mm
Width: 155 mm
Thickness: 16 mm
Weight
ISBN-13
978-3-319-34592-5 (9783319345925)
DOI
10.1007/978-3-319-01997-0
Schweitzer Classification
Saurabh Jain received the bachelor's and master's degrees from Indian Institute of Technology, Kanpur, India, in 2012 and 2013 respectively, the Ph.D. degree from National University of Singapore, Singapore, in 2018. After his Ph.D. he worked as a postdoctoral research fellow at the Department of Electrical and Computer Engineering of the National University of Singapore. Currently he is working as a research scientist at the processor architecture research lab (PARL) at Intel Labs, Bangalore.
His research interest includes development of reconfigurable architectures for widely voltage-scalable memory and logic and general purpose compute-in-memory.
Longyang Lin received the dual bachelor's degrees from Shenzhen University, Shenzhen, China and Umeå University, Umeå, Sweden, in 2011 and the master's degree from Lund University, Lund, Sweden, in 2013, and the Ph.D. degree from the National University of Singapore, Singapore, in 2018. He is currently a postdoctoral research fellow at the Department of Electrical and Computer Engineering of the National University of Singapore.
His research interests include ultra-low power VLSI circuits, self-powered sensor nodes, widely energy-scalable VLSI circuits and general purpose compute-in-memory.
Massimo Alioto received the Laurea (MSc) degree in Electronics Engineering and the Ph.D. degree in Electrical Engineering from the University of Catania (Italy) in 1997 and 2001, and the Bachelor of Music in Jazz Studies from the Conservatory of Music of Bologna in 2007. He is with the Department of Electrical and Computer Engineering, National University of Singapore where he leads the Green IC group and is the Director of the Integrated Circuits and Embedded Systems area. Previously, he held positions at the University of Siena, Intel Labs - CRL (2013), University of Michigan Ann Arbor (2011-2012), BWRC - University of California, Berkeley (2009-2011), and EPFL (Switzerland, 2007).
He has authored or co-authored more than 280 publications on journals and conference proceedings. He is co-author of four books, including Enabling the Internet of Things - from Circuits to Systems (Springer, 2017), Flip-Flop Design in Nanometer CMOS - from High Speed to Low Energy (Springer, 2015), and Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits (Springer, 2005). His primary research interests include self-powered wireless integrated systems, near-threshold circuits for green computing, widely energy- scalable and energy-quality scalable integrated systems, data-driven integrated systems, hardware-level security, and emerging technologies, among the others.
He is the Editor in Chief of the IEEE Transactions on VLSI Systems (2019-2020), and was the Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2018). In 2009-2010 he was Distinguished Lecturer of theIEEE Circuits and Systems Society, for which he is/was also member of the Board of Governors (2015-2020), and Chair of the "VLSI Systems and Applications" Technical Committee (2010-2012). In the last five years, he has given 50+ invited talks in top conferences, universities and leading semiconductor companies. His research has been mentioned in more than 60 press releases and popular science articles in the last two years. He served as Guest Editor of several IEEE journal special issues (e.g., TCAS-I, TCAS-II, JETCAS). He also serves or has served as Associate Editor of a number of IEEE and ACM journals. He is/was Technical Program Chair (ISCAS 2023, SOCC, ICECS, NEWCAS, VARI, ICM, PRIME) and Track Chair in a number of conferences (ICCD, ISCAS, ICECS, VLSI-SoC, APCCAS, ICM). Currently, he is also in the IEEE "Digital Architectures and Systems" ISSCC subcommittee, and the IEEE ASSCC technical program committee. Prof. Alioto is an IEEE Fellow.
