Many-Core Computing
Hardware and software
Published on 26. July 2019
Book
Hardback
600 pages
978-1-78561-582-5 (ISBN)
Description
Computing has moved away from a focus on performance-centric serial computation, instead towards energy-efficient parallel computation. This provides continued performance increases without increasing clock frequencies, and overcomes the thermal and power limitations of the dark-silicon era. As the number of parallel cores increases, we transition into the many-core computing era. There is considerable interest in developing methods, tools, architectures and applications to support many-core computing.
The primary aim of this edited book is to provide a timely and coherent account of the recent advances in many-core computing research. Starting with programming models, operating systems and their applications; the authors present runtime management techniques, followed by system modelling, verification and testing methods, and architectures and systems. The book ends with some examples of innovative applications.
The primary aim of this edited book is to provide a timely and coherent account of the recent advances in many-core computing research. Starting with programming models, operating systems and their applications; the authors present runtime management techniques, followed by system modelling, verification and testing methods, and architectures and systems. The book ends with some examples of innovative applications.
More details
Series
Language
English
Place of publication
Stevenage
United Kingdom
Target group
College/higher education
Professional and scholarly
Product notice
sewn/stitched
Cloth over boards
Dimensions
Height: 236 mm
Width: 165 mm
Thickness: 33 mm
Weight
1043 gr
ISBN-13
978-1-78561-582-5 (9781785615825)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Persons
Bashir M. Al-Hashimi is an international leader in the theory and practice of energy-efficient computing, undertaking fundamental and experimental research on hardware-software co-design for energy efficiency and hardware reliability. He is the Dean of the Faculty of Engineering and Physical Sciences, University of Southampton, UK, and founder and co-director of the Arm-ECS Research Centre. He was appointed Commander of the Order of the British Empire (CBE) in the 2018 Queen's Birthday Honours for services to computer engineering and to industry, elected Fellow of the Royal Academy of Engineering in 2013, and Fellow of the Institute of Electrical and Electronics Engineers in 2009. He has received a number of international awards, graduated 40 PhD students, and has published 400 technical papers and five research books.
Geoff V. Merrett is an Associate Professor at the School of Electronics and Computer Science at the University of Southampton, where he is head of the Centre for Internet of Things and Pervasive Systems. He is internationally known for his research into the system-level energy management of mobile and self-powered embedded systems, and he has published around 170 journal and conference papers in these areas. He was a co-investigator on the GBP5.6M PRiME Programme Grant on runtime power and reliability management of many-core systems, where he led the applications and cross-layer interaction theme. He was General Chair of the European Workshop on Microelectronics Education in 2016, is an Associate Editor for IET CDT, and is a member of the IET and IEEE.
Geoff V. Merrett is an Associate Professor at the School of Electronics and Computer Science at the University of Southampton, where he is head of the Centre for Internet of Things and Pervasive Systems. He is internationally known for his research into the system-level energy management of mobile and self-powered embedded systems, and he has published around 170 journal and conference papers in these areas. He was a co-investigator on the GBP5.6M PRiME Programme Grant on runtime power and reliability management of many-core systems, where he led the applications and cross-layer interaction theme. He was General Chair of the European Workshop on Microelectronics Education in 2016, is an Associate Editor for IET CDT, and is a member of the IET and IEEE.
Content
Part I: Programming models, OS and applications
Chapter 1: HPC with many core processors
Chapter 2: From irregular heterogeneous software to reconfigurable hardware
Chapter 3: Operating systems for many-core systems
Chapter 4: Decoupling the programming model from resource management in throughput processors
Chapter 5: Tools and workloads for many-core computing
Chapter 6: Hardware and software performance in deep learning
Part II: Runtime management
Chapter 7: Adaptive-reflective middleware for power and energy management in many-core heterogeneous systems
Chapter 8: Advances in power management of many-core processors
Chapter 9: Runtime thermal management of many-core systems
Chapter 10: Adaptive packet processing on CPU-GPU heterogeneous platforms
Chapter 11: From power-efficient to power-driven computing
Part III: System modelling, verification, and testing
Chapter 12: Modelling many-core architectures
Chapter 13: Power modelling of multicore systems
Chapter 14: Developing portable embedded software for multicore systems through formal abstraction and refinement
Chapter 15: Self-testing of multicore processors
Chapter 16: Advances in hardware reliability of reconfigurable many-core embedded systems
Part IV: Architectures and systems
Chapter 17: Manycore processor architectures
Chapter 18: Silicon photonics enabled rack-scale many-core systems
Chapter 19: Cognitive I/O for 3D-integrated many-core system
Chapter 20: Approximate computing across the hardware and software stacks
Chapter 21: Many-core systems for big-data computing
Chapter 22: Biologically-inspired massively-parallel computing
Chapter 1: HPC with many core processors
Chapter 2: From irregular heterogeneous software to reconfigurable hardware
Chapter 3: Operating systems for many-core systems
Chapter 4: Decoupling the programming model from resource management in throughput processors
Chapter 5: Tools and workloads for many-core computing
Chapter 6: Hardware and software performance in deep learning
Part II: Runtime management
Chapter 7: Adaptive-reflective middleware for power and energy management in many-core heterogeneous systems
Chapter 8: Advances in power management of many-core processors
Chapter 9: Runtime thermal management of many-core systems
Chapter 10: Adaptive packet processing on CPU-GPU heterogeneous platforms
Chapter 11: From power-efficient to power-driven computing
Part III: System modelling, verification, and testing
Chapter 12: Modelling many-core architectures
Chapter 13: Power modelling of multicore systems
Chapter 14: Developing portable embedded software for multicore systems through formal abstraction and refinement
Chapter 15: Self-testing of multicore processors
Chapter 16: Advances in hardware reliability of reconfigurable many-core embedded systems
Part IV: Architectures and systems
Chapter 17: Manycore processor architectures
Chapter 18: Silicon photonics enabled rack-scale many-core systems
Chapter 19: Cognitive I/O for 3D-integrated many-core system
Chapter 20: Approximate computing across the hardware and software stacks
Chapter 21: Many-core systems for big-data computing
Chapter 22: Biologically-inspired massively-parallel computing