Fault-Tolerance Techniques for Spacecraft Control Computers

 
 
Standards Information Network (Verlag)
  • 1. Auflage
  • |
  • erschienen am 23. Januar 2017
  • |
  • 376 Seiten
 
E-Book | PDF mit Adobe-DRM | Systemvoraussetzungen
978-1-119-10740-8 (ISBN)
 
Comprehensive coverage of all aspects of space application oriented fault tolerance techniques
* Experienced expert author working on fault tolerance for Chinese space program for almost three decades
* Initiatively provides a systematic texts for the cutting-edge fault tolerance techniques in spacecraft control computer, with emphasis on practical engineering knowledge
* Presents fundamental and advanced theories and technologies in a logical and easy-to-understand manner
* Beneficial to readers inside and outside the area of space applications
weitere Ausgaben werden ermittelt
Dr. Yang Mengfei, Professor, Chief Engineer and Chief Commander of China Academy of Space Technology, Beijing, China. Professor Yang Mengfei received his Master's degree in computer application from Beijing Institute of Control Engineering, China Academy of Space Technology in 1985. He then devoted himself to the research of fault tolerance computing, control of computer technology for space applications, and high-dependable software. In 2005, he received Ph.D. degree from Tsinghua University. Professor Yang has received numerous awards for his outstanding work and contribution to this sector.

Dr. Hua Gengxin, Professor, Chief Engineer, Beijing Institute of Control Engineering, Beijing, China.

Dr. Feng Yanjun, Senior Engineer, Director, China Academy of Space Technology, Beijing, China.

Dr. Gong Jian, Senior Engineer, Engineer in Charge, Beijing Institute of Control Engineering, Beijing, China.
1 - Title Page [Seite 5]
2 - Copyright Page [Seite 6]
3 - Contents [Seite 7]
4 - Brief Introduction [Seite 15]
5 - Preface [Seite 17]
6 - Chapter 1 Introduction [Seite 21]
6.1 - 1.1 Fundamental Concepts and Principles of Fault-tolerance Techniques [Seite 21]
6.1.1 - 1.1.1 Fundamental Concepts [Seite 21]
6.1.2 - 1.1.2 Reliability Principles [Seite 24]
6.1.2.1 - 1.1.2.1 Reliability Metrics [Seite 24]
6.1.2.2 - 1.1.2.2 Reliability Model [Seite 26]
6.2 - 1.2 The Space Environment and Its Hazards for the Spacecraft Control Computer [Seite 29]
6.2.1 - 1.2.1 Introduction to Space Environment [Seite 29]
6.2.1.1 - 1.2.1.1 Solar Radiation [Seite 29]
6.2.1.2 - 1.2.1.2 Galactic Cosmic Rays (GCRs) [Seite 30]
6.2.1.3 - 1.2.1.3 Van Allen Radiation Belt [Seite 30]
6.2.1.4 - 1.2.1.4 Secondary Radiation [Seite 32]
6.2.1.5 - 1.2.1.5 Space Surface Charging and Internal Charging [Seite 32]
6.2.1.6 - 1.2.1.6 Summary of Radiation Environment [Seite 33]
6.2.1.7 - 1.2.1.7 Other Space Environments [Seite 34]
6.2.2 - 1.2.2 Analysis of Damage Caused by the Space Environment [Seite 34]
6.2.2.1 - 1.2.2.1 Total Ionization Dose (TID) [Seite 34]
6.2.2.2 - 1.2.2.2 Single Event Effect (SEE) [Seite 35]
6.2.2.3 - 1.2.2.3 Internal/surface Charging Damage Effect [Seite 40]
6.2.2.4 - 1.2.2.4 Displacement Damage Effect [Seite 40]
6.2.2.5 - 1.2.2.5 Other Damage Effect [Seite 40]
6.3 - 1.3 Development Status and Prospects of Fault Tolerance Techniques [Seite 41]
6.4 - References [Seite 45]
7 - Chapter 2 Fault-Tolerance Architectures and Key Techniques [Seite 49]
7.1 - 2.1 Fault-tolerance Architecture [Seite 49]
7.1.1 - 2.1.1 Module-level Redundancy Structures [Seite 50]
7.1.2 - 2.1.2 Backup Fault-tolerance Structures [Seite 52]
7.1.2.1 - 2.1.2.1 Cold-backup Fault-tolerance Structures [Seite 52]
7.1.2.2 - 2.1.2.2 Hot-backup Fault-tolerance Structures [Seite 54]
7.1.3 - 2.1.3 Triple-modular Redundancy (TMR) Fault-tolerance Structures [Seite 56]
7.1.4 - 2.1.4 Other Fault-tolerance Structures [Seite 60]
7.2 - 2.2 Synchronization Techniques [Seite 60]
7.2.1 - 2.2.1 Clock Synchronization System [Seite 60]
7.2.1.1 - 2.2.1.1 Basic Concepts and Fault Modes of the Clock Synchronization System [Seite 60]
7.2.1.2 - 2.2.1.2 Clock Synchronization Algorithm [Seite 61]
7.2.2 - 2.2.2 System Synchronization Method [Seite 72]
7.2.2.1 - 2.2.2.1 The Real-time Multi-computer System Synchronization Method [Seite 72]
7.2.2.2 - 2.2.2.2 System Synchronization Method with Interruption [Seite 76]
7.3 - 2.3 Fault-tolerance Design with Hardware Redundancy [Seite 80]
7.3.1 - 2.3.1 Universal Logic Model and Flow in Redundancy Design [Seite 80]
7.3.2 - 2.3.2 Scheme Argumentation of Redundancy [Seite 81]
7.3.2.1 - 2.3.2.1 Determination of Redundancy Scheme [Seite 81]
7.3.2.2 - 2.3.2.2 Rules Obeyed in the Scheme Argumentation of Redundancy [Seite 82]
7.3.3 - 2.3.3 Redundancy Design and Implementation [Seite 83]
7.3.3.1 - 2.3.3.1 Basic Requirements [Seite 83]
7.3.3.2 - 2.3.3.2 FDMU Design [Seite 83]
7.3.3.3 - 2.3.3.3 CSSU Design [Seite 84]
7.3.3.4 - 2.3.3.4 IPU Design [Seite 85]
7.3.3.5 - 2.3.3.5 Power Supply Isolation Protection [Seite 87]
7.3.3.6 - 2.3.3.6 Testability Design [Seite 88]
7.3.3.7 - 2.3.3.7 Others [Seite 88]
7.3.4 - 2.3.4 Validation of Redundancy by Analysis [Seite 89]
7.3.4.1 - 2.3.4.1 Hardware FMEA [Seite 89]
7.3.4.2 - 2.3.4.2 Redundancy Switching Analysis (RSA) [Seite 89]
7.3.4.3 - 2.3.4.3 Analysis of the Common Cause of Failure [Seite 89]
7.3.4.4 - 2.3.4.4 Reliability Analysis and Checking of the Redundancy Power [Seite 90]
7.3.4.5 - 2.3.4.5 Analysis of the Sneak Circuit in the Redundancy Management Circuit [Seite 92]
7.3.5 - 2.3.5 Validation of Redundancy by Testing [Seite 93]
7.3.5.1 - 2.3.5.1 Testing by Failure Injection [Seite 93]
7.3.5.2 - 2.3.5.2 Specific Test for the Power of the Redundancy Circuit [Seite 94]
7.3.5.3 - 2.3.5.3 Other Things to Note [Seite 94]
7.4 - References [Seite 94]
8 - Chapter 3 Fault Detection Techniques [Seite 97]
8.1 - 3.1 Fault Model [Seite 97]
8.1.1 - 3.1.1 Fault Model Classified by Time [Seite 98]
8.1.2 - 3.1.2 Fault Model Classified by Space [Seite 98]
8.2 - 3.2 Fault Detection Techniques [Seite 100]
8.2.1 - 3.2.1 Introduction [Seite 100]
8.2.2 - 3.2.2 Fault Detection Methods for CPUs [Seite 101]
8.2.2.1 - 3.2.2.1 Fault Detection Methods Used for CPUs [Seite 102]
8.2.2.2 - 3.2.2.2 Example of CPU Fault Detection [Seite 103]
8.2.3 - 3.2.3 Fault Detection Methods for Memory [Seite 107]
8.2.3.1 - 3.2.3.1 Fault Detection Method for ROM [Seite 108]
8.2.3.2 - 3.2.3.2 Fault Detection Methods for RAM [Seite 111]
8.2.4 - 3.2.4 Fault Detection Methods for I/Os [Seite 115]
8.3 - References [Seite 116]
9 - Chapter 4 Bus Techniques [Seite 119]
9.1 - 4.1 Introduction to Space-borne Bus [Seite 119]
9.1.1 - 4.1.1 Fundamental Concepts [Seite 119]
9.1.2 - 4.1.2 Fundamental Terminologies [Seite 119]
9.2 - 4.2 The MIL-STD-1553B Bus [Seite 120]
9.2.1 - 4.2.1 Fault Model of the Bus System [Seite 121]
9.2.1.1 - 4.2.1.1 Bus-level Faults [Seite 123]
9.2.1.2 - 4.2.1.2 Terminal Level Faults [Seite 124]
9.2.2 - 4.2.2 Redundancy Fault-tolerance Mechanism of the Bus System [Seite 126]
9.2.2.1 - 4.2.2.1 The Bus-level Fault-tolerance Mechanism [Seite 127]
9.2.2.2 - 4.2.2.2 The Bus Controller Fault-tolerance Mechanism [Seite 128]
9.2.2.3 - 4.2.2.3 Fault-tolerance Mechanism of Remote Terminals [Seite 133]
9.3 - 4.3 The CAN Bus [Seite 136]
9.3.1 - 4.3.1 The Bus Protocol [Seite 137]
9.3.2 - 4.3.2 Physical Layer Protocol and Fault-tolerance [Seite 137]
9.3.2.1 - 4.3.2.1 Node Structure [Seite 137]
9.3.2.2 - 4.3.2.2 Bus Voltage [Seite 138]
9.3.2.3 - 4.3.2.3 Transceiver and Controller [Seite 139]
9.3.2.4 - 4.3.2.4 Physical Fault-tolerant Features [Seite 139]
9.3.3 - 4.3.3 Data Link Layer Protocol and Fault-tolerance [Seite 140]
9.3.3.1 - 4.3.3.1 Communication Process [Seite 140]
9.3.3.2 - 4.3.3.2 Message Sending [Seite 140]
9.3.3.3 - 4.3.3.3 The President Mechanism of Bus Access [Seite 140]
9.3.3.4 - 4.3.3.4 Coding [Seite 141]
9.3.3.5 - 4.3.3.5 Data Frame [Seite 141]
9.3.3.6 - 4.3.3.6 Error Detection [Seite 142]
9.4 - 4.4 The SpaceWire Bus [Seite 144]
9.4.1 - 4.4.1 Physical Layer Protocol and Fault-tolerance [Seite 146]
9.4.1.1 - 4.4.1.1 Connector [Seite 146]
9.4.1.2 - 4.4.1.2 Cable [Seite 146]
9.4.1.3 - 4.4.1.3 Low Voltage Differential Signal [Seite 146]
9.4.1.4 - 4.4.1.4 Data Filter (DS) Coding [Seite 148]
9.4.2 - 4.4.2 Data Link Layer Protocol and Fault-tolerance [Seite 149]
9.4.2.1 - 4.4.2.1 Packet Character [Seite 149]
9.4.2.2 - 4.4.2.2 Packet Parity Check Strategy [Seite 151]
9.4.2.3 - 4.4.2.3 Packet Structure [Seite 151]
9.4.2.4 - 4.4.2.4 Communication Link Control [Seite 151]
9.4.3 - 4.4.3 Networking and Routing [Seite 156]
9.4.3.1 - 4.4.3.1 Major Technique used by the SpaceWire Network [Seite 156]
9.4.3.2 - 4.4.3.2 SpaceWire Router [Seite 158]
9.4.4 - 4.4.4 Fault-tolerance Mechanism [Seite 159]
9.5 - 4.5 Other Buses [Seite 161]
9.5.1 - 4.5.1 The IEEE 1394 Bus [Seite 161]
9.5.2 - 4.5.2 Ethernet [Seite 163]
9.5.3 - 4.5.3 The I2C Bus [Seite 165]
9.6 - References [Seite 168]
10 - Chapter 5 Software Fault-Tolerance Techniques [Seite 171]
10.1 - 5.1 Software Fault-tolerance Concepts and Principles [Seite 171]
10.1.1 - 5.1.1 Software Faults [Seite 171]
10.1.2 - 5.1.2 Software Fault-tolerance [Seite 172]
10.1.3 - 5.1.3 Software Fault Detection and Voting [Seite 173]
10.1.4 - 5.1.4 Software Fault Isolation [Seite 174]
10.1.5 - 5.1.5 Software Fault Recovery [Seite 175]
10.1.6 - 5.1.6 Classification of Software Fault-tolerance Techniques [Seite 176]
10.2 - 5.2 Single-version Software Fault-tolerance Techniques [Seite 176]
10.2.1 - 5.2.1 Checkpoint and Restart [Seite 177]
10.2.2 - 5.2.2 Software-implemented Hardware Fault-tolerance [Seite 180]
10.2.2.1 - 5.2.2.1 Control Flow Checking by Software Signatures (CFCSS) [Seite 181]
10.2.2.2 - 5.2.2.2 Error Detection by Duplicated Instructions (EDDI) [Seite 184]
10.2.3 - 5.2.3 Software Crash Trap [Seite 185]
10.3 - 5.3 Multiple-version Software Fault-tolerance Techniques [Seite 185]
10.3.1 - 5.3.1 Recovery Blocks (RcB) [Seite 185]
10.3.2 - 5.3.2 N-version Programming (NVP) [Seite 187]
10.3.3 - 5.3.3 Distributed Recovery Blocks (DRB) [Seite 188]
10.3.4 - 5.3.4 N Self-checking Programming (NSCP) [Seite 189]
10.3.5 - 5.3.5 Consensus Recovery Block (CRB) [Seite 192]
10.3.6 - 5.3.6 Acceptance Voting (AV) [Seite 192]
10.3.7 - 5.3.7 Advantage and Disadvantage of Multiple-version Software [Seite 192]
10.4 - 5.4 Data Diversity Based Software Fault-tolerance Techniques [Seite 193]
10.4.1 - 5.4.1 Data Re-expression Algorithm (DRA) [Seite 193]
10.4.2 - 5.4.2 Retry Blocks (RtB) [Seite 194]
10.4.3 - 5.4.3 N-copy Programming (NCP) [Seite 194]
10.4.4 - 5.4.4 Two-pass Adjudicators (TPA) [Seite 195]
10.5 - References [Seite 197]
11 - Chapter 6 Fault-Tolerance Techniques for FPGA [Seite 199]
11.1 - 6.1 Effect of the Space Environment on FPGAs [Seite 200]
11.1.1 - 6.1.1 Single Event Transient Effect (SET) [Seite 201]
11.1.2 - 6.1.2 Single Event Upset (SEU) [Seite 201]
11.1.3 - 6.1.3 Single Event Latch-up (SEL) [Seite 202]
11.1.4 - 6.1.4 Single Event Burnout (SEB) [Seite 202]
11.1.5 - 6.1.5 Single Event Gate Rupture (SEGR) [Seite 202]
11.1.6 - 6.1.6 Single Event Functional Interrupt (SEFI) [Seite 203]
11.2 - 6.2 Fault Modes of SRAM-based FPGAs [Seite 203]
11.2.1 - 6.2.1 Structure of a SRAM-based FPGA [Seite 203]
11.2.2 - 6.2.2 Faults Classification and Fault Modes Analysis of SRAM-based FPGAs [Seite 206]
11.2.2.1 - 6.2.2.1 Faults Classification [Seite 206]
11.2.2.2 - 6.2.2.2 Fault Modes Analysis [Seite 206]
11.3 - 6.3 Fault-tolerance Techniques for SRAM-based FPGAs [Seite 210]
11.3.1 - 6.3.1 SRAM-based FPGA Mitigation Techniques [Seite 211]
11.3.1.1 - 6.3.1.1 The Triple Modular Redundancy (TMR) Design Technique [Seite 211]
11.3.1.2 - 6.3.1.2 The Inside RAM Protection Technique [Seite 213]
11.3.1.3 - 6.3.1.3 The Inside Register Protection Technique [Seite 214]
11.3.1.4 - 6.3.1.4 EDAC Encoding and Decoding Technique [Seite 215]
11.3.1.5 - 6.3.1.5 Fault Detection Technique Based on DMR and Fault Isolation Technique Based on Tristate Gate [Seite 218]
11.3.2 - 6.3.2 SRAM-based FPGA Reconfiguration Techniques [Seite 219]
11.3.2.1 - 6.3.2.1 Single Fault Detection and Recovery Technique Based on ICAP+FrameECC [Seite 219]
11.3.2.2 - 6.3.2.2 Multi-fault Detection and Recovery Technique Based on ICAP Configuration Read-back+RS Coding [Seite 225]
11.3.2.3 - 6.3.2.3 Dynamic Reconfiguration Technique Based on EAPR [Seite 230]
11.3.2.4 - 6.3.2.4 Fault Recovery Technique Based on Hardware Checkpoint [Seite 236]
11.3.2.5 - 6.3.2.5 Summary of Reconfiguration Fault?tolerance Techniques [Seite 237]
11.4 - 6.4 Typical Fault-tolerance Design of SRAM-based FPGA [Seite 239]
11.5 - 6.5 Fault-tolerance Techniques of Anti-fuse Based FPGA [Seite 247]
11.6 - References [Seite 250]
12 - Chapter 7 Fault-Injection Techniques [Seite 253]
12.1 - 7.1 Basic Concepts [Seite 253]
12.1.1 - 7.1.1 Experimenter [Seite 254]
12.1.2 - 7.1.2 Establishing the Fault Model [Seite 254]
12.1.3 - 7.1.3 Conducting Fault-injection [Seite 255]
12.1.4 - 7.1.4 Target System for Fault-injection [Seite 255]
12.1.5 - 7.1.5 Observing the System's Behavior [Seite 255]
12.1.6 - 7.1.6 Analyzing Experimental Findings [Seite 255]
12.2 - 7.2 Classification of Fault-injection Techniques [Seite 256]
12.2.1 - 7.2.1 Simulated Fault-injection [Seite 256]
12.2.1.1 - 7.2.1.1 Transistor Switch Level Simulated Fault-injection [Seite 257]
12.2.1.2 - 7.2.1.2 Logic Level Simulated Fault-injection [Seite 257]
12.2.1.3 - 7.2.1.3 Functional Level Simulated Fault-injection [Seite 257]
12.2.2 - 7.2.2 Hardware Fault-injection [Seite 258]
12.2.3 - 7.2.3 Software Fault-injection [Seite 260]
12.2.3.1 - 7.2.3.1 Injection During Compiling [Seite 260]
12.2.3.2 - 7.2.3.2 Injection During Operation [Seite 261]
12.2.4 - 7.2.4 Physical Fault-injection [Seite 262]
12.2.5 - 7.2.5 Mixed Fault-injection [Seite 264]
12.3 - 7.3 Fault-injection System Evaluation and Application [Seite 265]
12.3.1 - 7.3.1 Injection Controllability [Seite 265]
12.3.2 - 7.3.2 Injection Observability [Seite 266]
12.3.3 - 7.3.3 Injection Validity [Seite 266]
12.3.4 - 7.3.4 Fault-injection Application [Seite 267]
12.3.4.1 - 7.3.4.1 Verifying the Fault Detection Mechanism [Seite 267]
12.3.4.2 - 7.3.4.2 Fault Effect Domain Analysis [Seite 267]
12.3.4.3 - 7.3.4.3 Fault Restoration [Seite 267]
12.3.4.4 - 7.3.4.4 Coverage Estimation [Seite 267]
12.3.4.5 - 7.3.4.5 Delay Time [Seite 267]
12.3.4.6 - 7.3.4.6 Generating Fault Dictionary [Seite 268]
12.3.4.7 - 7.3.4.7 Software Testing [Seite 268]
12.4 - 7.4 Fault-injection Platform and Tools [Seite 268]
12.4.1 - 7.4.1 Fault-injection Platform in Electronic Design Automation (EDA) Environment [Seite 269]
12.4.2 - 7.4.2 Computer Bus-based Fault-injection Platform [Seite 272]
12.4.3 - 7.4.3 Serial Accelerator Based Fault-injection Case [Seite 274]
12.4.4 - 7.4.4 Future Development of Fault-injection Technology [Seite 276]
12.5 - References [Seite 278]
13 - Chapter 8 Intelligent Fault-Tolerance Techniques [Seite 281]
13.1 - 8.1 Evolvable Hardware Fault-tolerance [Seite 281]
13.1.1 - 8.1.1 Fundamental Concepts and Principles [Seite 281]
13.1.2 - 8.1.2 Evolutionary Algorithm [Seite 286]
13.1.2.1 - 8.1.2.1 Encoding Methods [Seite 290]
13.1.2.2 - 8.1.2.2 Fitness Function Designing [Seite 292]
13.1.2.3 - 8.1.2.3 Genetic Operators [Seite 293]
13.1.2.4 - 8.1.2.4 Convergence of Genetic Algorithm [Seite 297]
13.1.3 - 8.1.3 Programmable Devices [Seite 297]
13.1.3.1 - 8.1.3.1 ROM [Seite 298]
13.1.3.2 - 8.1.3.2 PAL and GAL [Seite 299]
13.1.3.3 - 8.1.3.3 FPGA [Seite 301]
13.1.3.4 - 8.1.3.4 VRC [Seite 302]
13.1.4 - 8.1.4 Evolvable Hardware Fault-tolerance Implementation Methods [Seite 305]
13.1.4.1 - 8.1.4.1 Modeling and Organization of Hardware Evolutionary Systems [Seite 306]
13.1.4.2 - 8.1.4.2 Reconfiguration and Its Classification [Seite 309]
13.1.4.3 - 8.1.4.3 Evolutionary Fault-tolerance Architectures and Methods [Seite 311]
13.1.4.4 - 8.1.4.4 Evolutionary Fault-tolerance Methods at Various Layers of the Hardware [Seite 313]
13.1.4.5 - 8.1.4.5 Method Example [Seite 318]
13.2 - 8.2 Artificial Immune Hardware Fault-tolerance [Seite 322]
13.2.1 - 8.2.1 Fundamental Concepts and Principles [Seite 322]
13.2.1.1 - 8.2.1.1 Biological Immune System and Its Mechanism [Seite 324]
13.2.1.2 - 8.2.1.2 Adaptive Immunity [Seite 325]
13.2.1.3 - 8.2.1.3 Artificial Immune Systems [Seite 327]
13.2.1.4 - 8.2.1.4 Fault-tolerance Principle of Immune Systems [Seite 330]
13.2.2 - 8.2.2 Fault-tolerance Methods with Artificial Immune System [Seite 334]
13.2.2.1 - 8.2.2.1 Artificial Immune Fault-tolerance System Architecture [Seite 336]
13.2.2.2 - 8.2.2.2 Immune Object [Seite 338]
13.2.2.3 - 8.2.2.3 Immune Control System [Seite 341]
13.2.2.4 - 8.2.2.4 Working Process of Artificial Immune Fault-tolerance System [Seite 345]
13.2.3 - 8.2.3 Implementation of Artificial Immune Fault-tolerance [Seite 348]
13.2.3.1 - 8.2.3.1 Hardware [Seite 348]
13.2.3.2 - 8.2.3.2 Software [Seite 350]
13.3 - References [Seite 354]
14 - Acronyms [Seite 357]
15 - Index [Seite 363]
16 - EULA [Seite 373]

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