Millimeter-Wave Digitally Intensive Frequency Generation in CMOS

Academic Press
  • 1. Auflage
  • |
  • erschienen am 23. September 2015
  • |
  • 200 Seiten
E-Book | ePUB mit Adobe DRM | Systemvoraussetzungen
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978-0-12-802361-7 (ISBN)

This book describes the digitally intensive time-domain architectures and techniques applied to millimeter-wave frequency synthesis, with the objective of improving performance and reducing the cost of implementation. Coverage includes system architecture, system level modeling, critical building block design, and digital calibration techniques, making it highly suitable for those who want to learn about mm-wave frequency generation for communication and radar applications, integrated circuit implementation, and time-domain circuit and system techniques.

  • Highlights the challenges of frequency synthesis at mm-wave band using CMOS technology
  • Compares the various approaches for mm-wave frequency generation (pros and cons)
  • Introduces the digitally intensive synthesizer approach and its advantages
  • Discusses the proper partitioning of the digitally intensive mm-wave frequency synthesizer into mm-wave, RF, analog, digital and software components
  • Provides detailed design techniques from system level to circuit level
  • Addresses system modeling, simulation techniques, design-for-test, and layout issues
  • Demonstrates the use of time-domain techniques for high-performance mm-wave frequency synthesis

Wanghua Wu finished her PhD at the University of Delft in 2013 where she designed the first-ever 60-GHz all-digital PLL (ADPLL) with programmable wideband frequency modulation capability in 65-nm CMOS (from system modeling to IC implementation and testing software development). In 2013 she won the second-prize award in the Broadcom University Research competition for the Ph.D. work on 60-GHz all-digital PLL. She is currently a design engineer at Marvell Semiconductor Inc.
  • Englisch
  • San Diego
  • |
  • USA
Elsevier Science
  • 7,40 MB
978-0-12-802361-7 (9780128023617)
0-12-802361-9 (0128023619)
weitere Ausgaben werden ermittelt
  • Front Cover
  • Millimeter-Wave Digitally Intensive Frequency Generation in CMOS
  • Copyright Page
  • Contents
  • Preface
  • List of Abbreviations
  • 1 Introduction
  • 1.1 Motivation
  • 1.1.1 Advantages of Millimeter-Wave Radios
  • 1.1.2 Deep-Submicron CMOS
  • 1.1.3 Digitally Intensive Approach
  • 1.2 Design Challenges
  • 1.2.1 Toward All-Digital PLL in mm-Wave Regime
  • 1.2.2 Wide Tuning Range and Fine Frequency Resolution
  • 1.2.3 Linear Wideband FM
  • References
  • 2 Millimeter-Wave Frequency Synthesizers
  • 2.1 Frequency Synthesizer Fundamentals
  • 2.1.1 PN in Oscillators
  • 2.1.2 Frequency Synthesizer in a Radio Transceiver
  • 2.1.3 Methods for Frequency Synthesis
  • 2.2 Phase-Locked Loop
  • 2.2.1 Charge-Pump PLL
  • 2.2.2 All-Digital PLL
  • 2.3 Millimeter-Wave PLL Architectures
  • 2.3.1 PLL with a Fundamental Oscillator
  • 2.3.2 PLL-Based Harmonic Generation
  • 2.4 Summary
  • References
  • 3 Circuit Design Techniques for mm-Wave Frequency Synthesizer
  • 3.1 Wideband Oscillator
  • 3.1.1 Oscillator with Switched-Capacitor Tuning
  • 3.1.2 Oscillator with Switched-Inductor Tuning
  • 3.1.3 Transformer-Coupled Oscillator
  • 3.2 High-Frequency Divider
  • 3.2.1 Regenerative Frequency Divider
  • 3.2.2 CML Divider
  • 3.2.3 Digital CMOS Divider
  • 3.3 Frequency Multiplier
  • 3.4 Summary
  • References
  • 4 All-Digital Phase-Locked Loop
  • 4.1 Phase-Domain Operation
  • 4.2 Reference Clock Retiming
  • 4.3 DCO Gain Normalization and Estimation
  • 4.4 Loop Gain Factor and Gear Shifting of the PLL Gain
  • 4.4.1 Loop Gain Factor
  • 4.4.2 Gear Shifting PLL Gain
  • 4.5 PLL Frequency Response
  • 4.6 Noise and Error Sources
  • 4.7 Behavioral Modeling and Simulation Approach
  • 4.8 Summary
  • References
  • 5 Millimeter-Wave Digitally Controlled Oscillator
  • 5.1 From Low-Gigahertz DCOs to mm-Wave DCOs
  • 5.2 Reconfigurable Resonator with Distributed Metal Capacitors
  • 5.3 Fine-Tuning Techniques to Achieve High-Frequency Resolution
  • 5.3.1 Inductor with Distributed Switched-C for Fine-Tuning
  • 5.3.2 Transformer-Coupled Fine-Tuning Bank
  • 5.4 Example Implementation of 60-GHz DCOs
  • 5.4.1 L-DCO
  • 5.4.2 T-DCO
  • 5.4.3 Experiment Results
  • Differential TL Test Structure
  • L-DCO Measurement Results
  • T-DCO Measurement Results
  • 5.5 Summary
  • References
  • 6 Application: A 60-GHz All-Digital PLL for FMCW Transmitter Applications
  • 6.1 Design Specification
  • 6.1.1 Frequency Modulation Range (BW)
  • 6.1.2 Frequency Modulation Period (Tmod)
  • 6.1.3 Phase Noise
  • 6.1.4 Frequency Sweep Linearity and Quantization Effect
  • 6.2 Multi-Rate ADPLL-Based Frequency Modulator
  • 6.2.1 60-GHz ADPLL
  • 6.2.2 Wideband Frequency Modulation
  • 6.3 DCO Interfacing
  • 6.3.1 Separate DCO Fine-Tuning Bank for CW and FM
  • 6.3.2 Decoder Mapping Algorithm for Device Matching
  • 6.4 Divider Chain Design
  • 6.4.1 Circuit Design
  • 6.4.2 Simulated Performance
  • 6.5 TDC Design and Calibration
  • 6.5.1 TDC Core Architecture
  • 6.5.2 TDC Unit Cell Design
  • 6.5.3 TDC Calibration
  • 6.5.4 Simulated Performance
  • 6.6 Reference Slicer Design
  • 6.6.1 Circuit Design
  • 6.6.2 Simulated Performance
  • 6.7 Phase Error Generation and Glitch Removal
  • 6.8 Top-Level Floor Plan Considerations for mm-Wave ADPLL
  • 6.9 Experiment Results for 60-GHz ADPLL
  • 6.10 Summary
  • References
  • 7 Digital Techniques for Higher RF Performance
  • 7.1 Frequency Tuning Nonlinearity in a Multibank DCO
  • 7.2 Multibank DCO Gain Calibration and Linearization
  • 7.3 Mismatch Calibration of the Fine-Tuning Bank
  • 7.4 Synchronization in a Multirate System
  • 7.5 Experimental Results of FMCW Transmitter
  • 7.5.1 FSK Modulation
  • 7.5.2 FMCW Modulation
  • 7.6 Summary
  • References
  • 8 Design for Test of the mm-Wave ADPLL
  • 8.1 Testing Challenges for the RF Synthesizer
  • 8.2 Critical Signals in ADPLL for DFT and DFC
  • 8.3 DFT Techniques for ADPLL
  • 8.3.1 Snapshotting Internal Signals for DFT and DFC
  • 8.3.2 Performance-Based BIST and BISC
  • DCO Tuning Step Analyzer
  • Built-in Phase Error (FE) Analyzer
  • 8.4 Measurement Setup and Procedures
  • 8.4.1 Measurement Setup
  • 8.4.2 Test Procedures and Test Modes
  • 8.5 Summary
  • References
  • Index
  • Back Cover
Chapter 2

Millimeter-Wave Frequency Synthesizers

This chapter reviews the basics of frequency synthesizer design. It begins with an introduction to frequency synthesizer fundamentals in Section 2.1. The operation of both analog and all-digital phase-locked loops is presented in Section 2.2. Section 2.3 compares two frequency synthesizer topologies that are most commonly employed for mm-wave frequency generation: phase-locked loop (PLL) with a fundamental oscillator and PLL-based harmonic generation. Both of the synthesizer topologies can be made digitally intensive using the architecture and digital techniques that will be described in Chapters 4-8.


Phase noise; phase-locked loop (PLL); direct digital frequency synthesizer (DDFS); charge-pump; all-digital phase-locked loop (ADPLL); millimeter-wave; harmonic generation


2.1 Frequency Synthesizer Fundamentals 17

2.1.1 PN in Oscillators 18

2.1.2 Frequency Synthesizer in a Radio Transceiver 20

2.1.3 Methods for Frequency Synthesis 21

2.2 Phase-Locked Loop 23

2.2.1 Charge-Pump PLL 24

2.2.2 All-Digital PLL 26

2.3 Millimeter-Wave PLL Architectures 28

2.3.1 PLL with a Fundamental Oscillator 28

2.3.2 PLL-Based Harmonic Generation 29

2.4 Summary 32

References 33

2.1 Frequency Synthesizer Fundamentals

A local oscillator (LO) is required in high-performance radio transceivers irrespective of the architecture. It is employed to translate the RF signal down to an intermediate frequency or baseband in receivers, and vice versa in transmitters. The LO has to be tunable across the RF band and the frequency resolution has to be at least equal to the channel spacing. A frequency synthesizer is typically used as the LO in RF transceivers to overcome the drifts in oscillator frequency due to temperature variations. The synthesizer provides a stable RF carrier with high spectral purity, ideally across a wide frequency span. RF frequency synthesizers remain one of the most challenging blocks in many wireless systems (e.g., mobile communications). The choice of frequency synthesis approach depends on factors such as phase noise (PN), permissible spurious output levels, switching rate, frequency resolution, cost, and complexity.

2.1.1 PN in Oscillators

An ideal LO operating at angular frequency c, produces a sinusoidal output versus time of the form (t)=A·cos(?ct+f), where A is the amplitude and is an arbitrary and fixed phase. The zero-crossings occur at integer multiples of the period, c=2p/?c. In the frequency domain, all of its power is concentrated at a single frequency, c, as shown in Figure 2.1a. However, noise sources inside practical oscillator circuits (e.g., from transistors) perturb the zero crossings randomly. Therefore, both the amplitude and phase vary randomly with time. In most cases, the change in amplitude is removed by a limiting buffer circuit, and therefore only the random deviation of the phase must be considered:

(t)=AL·cos(?ct+fn(t)), (2.1)


where n(t) is a small, random phase quantity that causes the zero crossings to deviate from integer multiples of c. Consequently, the oscillator frequency spectrum spreads around c (Figure 2.1b). The phase function n(t) in the time domain is observed as spectral spreading in the frequency domain and is called PN [1].

Figure 2.1 Output spectrum of (a) ideal and (b) practical oscillators.

PN of RF oscillators is normally characterized in the frequency domain. For a small value of the phase fluctuation, fn(t)|«1 radian, Eq. (2.1) can be simplified to

(t)~A·cos(?ct)-A·fn(t)·sin(?ct), (2.2)


which means that the spectrum of n(t) is frequency-translated to ?c. Thus, the declining skirts in Figure 2.1b are due to the phase fluctuation n(t). This PN can be quantified by considering a 1-Hz bandwidth at an offset ? from the carrier, calculating the noise power, and dividing that result by the carrier power [2].

(??)=10log10noisepowerina1-Hzbandwidthat?c+??carrierpower. (2.3)


This is the single-sided spectral noise density, usually expressed in decibels, with respect to the carrier per hertz bandwidth (i.e., dBc/Hz). The single-sided PN of Eq. (2.3) is one-half of the PN spectrum, which contains both upper- and lower-frequency components (c±??). In practice, the PN reaches a constant floor at large frequency offsets (e.g., ? larger than a few tens of megahertz in a typical RF oscillator). The region near the carrier is called "close-in" PN and the region far from the carrier is called "far-out" PN, although the border between the two is vague. In this book, "far-out" PN refers to offsets greater than 20 MHz from the carrier.

Figure 2.2 shows a PN spectrum of a typical oscillator. In this log-log plot, the PN in dBc/Hz is plotted against the offset ? from the carrier frequency c. The PN profile traverses through /?3, /?2, and /?0 slope regions. The region /?2 is generally referred to as the thermal noise region because it is caused by white or uncorrelated timing fluctuations in the period of oscillation. The 1/f flicker noise of electronic devices is also substantial for lower offset frequencies. It gets up-converted and creates the /?3 region. Finally, the /?0 region is typically dominated by the thermal noise added outside the oscillator proper, such as in an output buffer.

Figure 2.2 PN spectrum of a typical oscillator.

In addition, an undesired, systematic fluctuation in the oscillator PN gives rise to a spurious tone. This can be simply explained by considering the effect of a single sinusoidal tone on the phase n(t)=fpsin(?mt). Then, Eq. (2.2) becomes

(t)~A·cos(?ct)+A·fp2[cos(?c+?m)t-cos(?c-?m)t], (2.4)


which indicates that the single sideband PN has a spurious tone at ?=?m. Spurious tones (or spurs) in a PN spectrum of an oscillator are normally caused by a parasitic coupling from the frequency reference circuitry, phase/frequency detector (PFD) and the charge-pump in classical phase-locked loop (PLL)-based synthesizers. In the time domain, the presence of systematic timing fluctuations in an oscillator waveform represents a periodic timing error. In the frequency domain, it manifests itself as undesired tones in the frequency spectrum. Ideally, the oscillator output spectrum is centered at a single frequency with no spurious tones, as shown in Figure 2.1a. In reality, the presence of spurious tones causes other frequency components to appear in the oscillator output spectrum (see the spurious tones in Figure 2.1b). The amplitude of spurious tones is specified relative to the LO carrier power (i.e., in dBc) at a specific frequency offset from the carrier. It is simply the ratio of the powers of spurious tone and carrier.

2.1.2 Frequency Synthesizer in a Radio Transceiver

The design of RF synthesizers remains one of the most challenging tasks because the synthesizer must operate at a low supply voltage of today's CMOS technologies, while meeting stringent PN and switching transient specifications with low cost and power consumption. We can generally evaluate a synthesizer design by considering the following criteria (in order of importance): PN at a specified offset from the carrier, discrete spurious tones levels, switching speed (defined by the time it takes the synthesizer to hop from its stable state f0, by a certain frequency excursion ?f, and converge to the new frequency f0±?f), frequency and tuning range, level of integration, and portability between technology nodes.

For wireless applications, a transmitter's PN can cause interference in adjacent bands and distort phase-modulated signals in the process of up/down-conversion, since the PN is indistinguishable from phase or frequency modulation. The resultant constellation points experience small random rotations around the origin, which degrade the error vector magnitude, (EVM; i.e., a measure used to quantify modulation performance of a digital radio transceiver), especially when complex modulation (i.e., I-Q) schemes are employed,...

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